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PDF SP7800AJN Data sheet ( Hoja de datos )
| Número de pieza | SP7800AJN | |
| Descripción | 12-Bit 3ms Sampling A/D Converter | |
| Fabricantes | Sipex | |
| Logotipo |  |
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® SP7800A
12-Bit 3µs Sampling A/D Converter
s 333k Samples Per Second
s Standard ±10V and ±5V Input
s No Missing Codes Over Temperature
s AC Performance Over Temperature
71.5dB Signal–to–Noise Ratio at Nyquist
85dB Spurious–free Dynamic Range at
49KHz
–81dB Total Harmonic Distortion at
49KHz
s Internal Sample/Hold, Reference,
Clock, and 3-State Outputs
s Power Dissipation: 90mW
s 24–Pin Narrow DIP and 24–Lead SOIC
s Enhanced Single (+5V) Supply Version of
ADS7800
DESCRIPTION…
The SP7800A is a complete 12-bit sampling A/D converter using state–of–the–art CMOS structures.
It contains a complete 12–bit successive approximation A/D converter with internal sample/hold,
reference, clock, digital interface for microprocessor control, and three–state output drivers. AC and
DC performance are completely specified. Two grades based on linearity and dynamic performance
are available to provide the optimum price/performance fit in a wide range of applications.
±10VIN
±5VIN
CS R/C HBE
Control
Logic
Clock
IBIP
CDAC.....
.....
Internal
Ref
.....
.....
SAR
Comparator
Output
Latches
And
Three
State
Drivers
BUSY
Three
State
Parallel
Output
Data
Bus
SP7800ADS/02
SP7800A 12-Bit 3µs Sampling A/D Converter
1
© Copyright 2000 Sipex Corporation
1 page  
ing resistors provide industry–standard input ranges
of ±5V or ±10V. The 24-pin SP7800A is available in
plastic DIP, and SOIC packages and it operates from
a single +5V supply. The SP7800A is available in
grades specified over the 0°C to +70°C commercial
temperature ranges.
OPERATION...
Basic Operation
Figure 1 shows the simple hookup circuit required
to operate the SP7800A in a ±10V range in the
Convert Mode. A convert command arriving on
R/C, (a pulse taking R/C LOW for a minimum of
40ns) puts the SP7800A in the HOLD mode, and
a conversion is started. The falling edge of R/C
establishes the sampling instant of the A/D; it must
therefore have very low jitter. BUSY will be held
LOW during the conversion, and rises only after
the conversion is completed and the data has been
transferred to the output drivers. Thus, the rising
edge can be used to read the data from the conver-
sion. Also, during conversion, the BUSY signal
putstheoutputdatalinesin Hi-Zstatesandinhibits
the input lines. This means that pulses on R/C are
ignored, so that new conversions cannot be initi-
ated during a conversion, either as a result of
spurious signals or to short-cycle the SP7800A.
In the Read Mode, the input to R/C is kept nor-
mally LOW, and a HIGH pulse is used to read data
and initiate a conversion. In this mode, the rising
Input
D11
(MSB)
1 IN 1
2 IN 2
+5V
+5V 24
+5V 23
6.8µF +
0.1µF
3 N.C.
N.C. 22
4 AGND BUSY 21
5 D11 (MSB) CS 20
Busy
6 D10
7 D9
R/C 19
HBE 18
Convert
Command
8 D8 D0 (LSB) 17
9 D7
D1 16
10 D6
D2 15
11 D5
D3 14
12 D4
DGND 13
Data
Out
D0
(LSB)
Figure 1. Basic ±10V Operation
edge of R/C will enable the output data pins, and
the data from the previous conversion becomes
valid. The falling edge then puts the SP7800A in
a hold mode, and initiates a new conversion.
The SP7800A will begin acquiring a new sample
just prior to BUSY output rising, and will track the
input signal until the next conversion is started.
For use with an 8-bit bus, the data can be read out
in two bytes under the control of HBE. With a
LOW input on HBE, at the end of a conversion, the
8 LSBs of data are loaded into the output drivers D7
– D4 and D3–D0. Taking HBE HIGH then loads the
4 MSBs on output drivers D3–D0, with D7–D4
being forced LOW.
Analog Input Ranges
The SP7800A offers two standard bipolar input
ranges: ±10V and ±5V. If a ±10V range is re-
quired, the analog input signal should be con-
nected to pin 1. A signal requiring a ±5V range
should be connected to pin 2. In either case, the
other pin of the two must be grounded or connected
to the adjustment circuits described in the section
on calibration.
Controlling The SP7800A
The SP7800A can be easily interfaced to most
microprocessor-based and other digital systems. The
microprocessor may take full control of each conver-
sion, or the SP7800A may operate in a stand-alone
mode, controlled only by the R/C input. Full control
consists of initiating the conversion and reading the
output data at user command, transmitting data either
all 12-bits in one parallel word, or in two 8-bit bytes.
The three control inputs (CS, R/C and HBE) are all
TTL/CMOS compatible. The functions of the control
lines are shown in Table 1.
For stand-alone operation, control of the SP7800A
is accomplished by a single control line connected
to R/C. In this mode, CS and HBE are connected
to GND. The output data are presented as 12-bit
words. The stand-alone mode is used in systems
containing dedicated input ports which do not
require full bus interface capability.
ConversionisinitiatedbyaHIGH-to-LOWtransition
SP7800ADS/02
SP7800A 12-Bit 3µs Sampling A/D Converter
5
© Copyright 2000 Sipex Corporation
5 Page 
PACKAGE: PLASTIC
DUAL–IN–LINE
(NARROW)
E1 E
D1 = 0.005" min.
(0.127 min.)
D
e = 0.100 BSC
(2.540 BSC)
B1
B
ALTERNATE
END PINS
(BOTH ENDS)
A1 = 0.015" min.
(0.381min.)
A = 0.210" max.
(5.334 max).
A2
L
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
24–PIN
A2 0.115/0.195
(2.921/4.953)
B 0.014/0.023
(0.356/0.584)
B1 0.045/0.070
(1.143/1.778)
C 0.008/0.014
(0.203/0.356)
D 1.155/1.280
(29.33/32.51)
E 0.300/0.325
(7.620/8.255)
E1 0.240/0.280
(6.096/7.112)
L 0.115/0.150
(2.921/3.810)
Ø 0°/ 15°
(0°/15°)
28–PIN
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
1.385/1.454
(35.17/36.90)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0°/ 15°
(0°/15°)
C
Ø
eA = 0.300 BSC
(7.620 BSC)
SP7800ADS/02
SP7800A 12-Bit 3µs Sampling A/D Converter
11
© Copyright 2000 Sipex Corporation
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SP7800AJN.PDF ] | |
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