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PDF MMDF3N06HD Data sheet ( Hoja de datos )
| Número de pieza | MMDF3N06HD | |
| Descripción | DUAL TMOS POWER MOSFET 60 VOLTS | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMDF3N06HD/D
Advance Information
Medium Power Surface Mount Products
TMOS Dual N-Channel
Field Effect Transistors
Dual HDTMOS are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density TMOS process. These
miniature surface mount MOSFETs feature low RDS(on) and true
logic level performance. Dual HDTMOS devices are designed for
use in low voltage, high speed switching applications where power
efficiency is important. Typical applications are dc–dc converters,
and power management in portable and battery powered products
such as computers, printers, cellular and cordless phones. They
can also be used for low voltage motor controls in mass storage
products such as disk drives and tape drives.
• Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs
• Miniature SO–8 Surface Mount Package — Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Mounting Information for SO–8 Package Provided
G
D
D
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C
Source Current — Continuous @ TA = 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 60 Vdc, VGS = 5.0 Vdc, VDS = 32 Vdc, IL = 15 Apk, L = 10 mH, RG = 25 Ω)
Thermal Resistance — Junction–to–Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
DEVICE MARKING
D3N06
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMDF3N06HDR2
13″
12 mm embossed tape
2500 units
(1) Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.
™
S
S
MMDF3N06HD
Motorola Preferred Device
DUAL TMOS
POWER MOSFET
60 VOLTS
RDS(on) = 100 mW
CASE 751–05, Style 11
SO–8
Source–1
Gate–1
Source–2
Gate–2
18
27
36
45
Top View
Drain–1
Drain–1
Drain–2
Drain–2
Symbol
VDSS
VGS
ID
IDM
IS
PD
TJ, Tstg
EAS
RθJA
TL
Value
60
± 20
3.3
16.5
1.7
2.0
– 55 to 150
105
62.5
260
Unit
Vdc
Vdc
Adc
Apk
Adc
Watts
°C
mJ
°C/W
°C
This document contains information on a new product. Specifications and information herein are subject to change without notice.
HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
©MMoottoororolal,aInTc.M19O9S7 Power MOSFET Transistor Device Data
1
1 page  
MMDF3N06HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 9). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
1200
Ciss
1000
TJ = 25°C
800
Crss
600
400
Ciss
200
0
–10
Coss
–5.0 0 5.0 10 15 20 25
VGS VDS
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 8. Capacitance Variation
30
1000
VDD = 30 V
ID = 3.0 A
VGS = 10 V
TJ = 25°C
100
td(off)
10 tf
tr
td(on)
12
11
10
9.0
8.0
7.0
6.0
5.0
4.0 Q1
3.0
2.0
1.0 Q3
0
0 2.0
30
QT
VGS
20
Q2 10
VDS
4.0 6.0 8.0 10
ID = 3.0 A
TJ = 25°C
12 14
Qg, TOTAL GATE CHARGE (nC)
0
16
Figure 9. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
2.5
TJ = 25°C
2.0 VGS = 0 V
1.5
1.0
0.5
1.0
1.0
10
RG, GATE RESISTANCE (OHMS)
100
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
0
0.5 0.55 0.6 0.65 0.7 0.75
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage
versus Current
0.8
Motorola TMOS Power MOSFET Transistor Device Data
5
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