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PDF MM74HC161 Data sheet ( Hoja de datos )
| Número de pieza | MM74HC161 | |
| Descripción | Synchronous Binary Counter with Asynchronous Clear . Synchronous Binary Counter with Synchronous Clear | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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September 1983
Revised February 1999
MM74HC161 • MM74HC163
Synchronous Binary Counter with Asynchronous Clear
• Synchronous Binary Counter with Synchronous Clear
General Description
The MM74HC161 and MM74HC163 synchronous presetta-
ble counters utilize advanced silicon-gate CMOS technol-
ogy and internal look-ahead carry logic for use in high
speed counting applications. They offer the high noise
immunity and low power consumption inherent to CMOS
with speeds similar to low power Schottky TTL. The HC161
and the HC163 are 4 bit binary counters. All flip-flops are
clocked simultaneously on the LOW-to-HIGH transition
(positive edge) of the CLOCK input waveform.
These counters may be preset using the LOAD input. Pre-
setting of all four flip-flops is synchronous to the rising edge
of CLOCK. When LOAD is held LOW counting is disabled
and the data on the A, B, C, and D inputs is loaded into the
counter on the rising edge of CLOCK. If the load input is
taken HIGH before the positive edge of CLOCK the count
operation will be unaffected.
All of these counters may be cleared by utilizing the
CLEAR input. The clear function on the MM74HC163
counter is synchronous to the clock. That is, the counters
are cleared on the positive edge of CLOCK while the clear
input is held LOW.
The MM74HC161 counter is cleared asynchronously.
When the CLEAR is taken LOW the counter is cleared
immediately regardless of the CLOCK.
Two active HIGH enable inputs (ENP and ENT) and a RIP-
PLE CARRY (RC) output are provided to enable easy cas-
cading of counters. Both ENABLE inputs must be HIGH to
count. The ENT input also enables the RC output. When
enabled, the RC outputs a positive pulse when the counter
overflows. This pulse is approximately equal in duration to
the HIGH level portion of the QA output. The RC output is
fed to successive cascaded stages to facilitate easy imple-
mentation of N-bit counters.
All inputs are protected from damage due to static dis-
charge by diodes to VCC and ground.
Features
s Typical operating frequency: 40 MHz
s Typical propagation delay; clock to Q: 18 ns
s Low quiescent current: 80 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Wide power supply range: 2–6V
Ordering Code:
Order Number Package Number
Package Description
MM74HC161M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC161SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC161MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC161N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC163M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC163SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC163MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC163N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS005008.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
VCC
TA=25°C
TA=−40 to 85°C TA=−55 to 125°C
Typ Guaranteed Limits
tS Minimum Setup
Time Enable
2.0V
4.5V
175 220
35 44
260
52
to Clock
6.0V
30 37
44
tH Minimum Hold Time
Data from Clock
2.0V
4.5V
50 63
10 13
75
15
6.0V
9 11
13
tH Minimum Hold Time
Enable, Load or Clear
2.0V
4.5V
00
00
0
0
to Clock
6.0V
00
0
tW Minimum Pulse Width
Clock, Clear, or
2.0V
4.5V
80 100
16 20
120
24
Load
6.0V
14 17
20
tTLH, tTHL
Maximum
Output Rise and
2.0V
4.5V
40
8
75
15
95
19
110
22
Fall Time
6.0V
7
13
16
19
tr, tf Maximum Input Rise
and Fall Time
2.0V
1000
4.5V
500
500
1000
500
1000
500
6.0V
400 400
400
CPD Powert Dissipation
Capacitance (Note 5)
(per package)
90
CIN Maximum Input Capacitance
5 10
10
10
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
Logic Waveforms
Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences
Sequence: (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one and two (4) Inhibit
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MM74HC161.PDF ] | |
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