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PDF MM74HC123A Data sheet ( Hoja de datos )
| Número de pieza | MM74HC123A | |
| Descripción | Dual Retriggerable Monostable Multivibrator | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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September 1983
Revised February 1999
MM74HC123A
Dual Retriggerable Monostable Multivibrator
General Description
The MM74HC123A high speed monostable multivibrators
(one shots) utilize advanced silicon-gate CMOS technol-
ogy. They feature speeds comparable to low power Schot-
tky TTL circuitry while retaining the low power and high
noise immunity characteristic of CMOS circuits.
Each multivibrator features both a negative, A, and a posi-
tive, B, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken low resets the one shot. The MM74HC123A
can be triggered on the positive transition of the clear while
A is held LOW and B is held HIGH.
The MM74HC123A is retriggerable. That is it may be trig-
gered repeatedly while their outputs are generating a pulse
and the pulse will be extended.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques. The out-
put pulse equation is simply: PW = (REXT) (CEXT); where
PW is in seconds, R is in ohms, and C is in farads. All
inputs are protected from damage due to static discharge
by diodes to VCC and ground.
Features
s Typical propagation delay: 25 ns
s Wide power supply range: 2V–6V
s Low quiescent current: 80 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads
s Simple pulse width formula T = RC
s Wide pulse range: 400 ns to ∞ (typ)
s Part to part variation: ±5% (typ)
s Schmitt Trigger A & B inputs enable infinite signal input
rise and fall times.
Ordering Code:
Order Number Package Number
Package Description
MM74HC123AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC123ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC123AMTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC123AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Timing Component
Pin Assignment for DIP, SOIC, SOP and TSSOP
Note: Pin 6 and Pin 14 must be hard-wired to GND.
Top View
© 1999 Fairchild Semiconductor Corporation DS005206.prf
www.fairchildsemi.com
1 page  
Theory of Operation
1POSITIVE EDGE TRIGGER
2NEGATIVE EDGE TRIGGER
3POSITIVE EDGE TRIGGER
4POSITIVE EDGE RE-TRIGGER (PULSE LENGTHENING)
5RESET PULSE SHORTENING
6CLEAR TRIGGER
FIGURE 1.
TRIGGER OPERATION
As shown in Figure 1 and the logic diagram, before an
input trigger occurs, the one shot is in the quiescent state
with the Q output LOW, and the timing capacitor CEXT com-
pletely charged to VCC. When the trigger input A goes from
VCC to GND (while inputs B and clear are held to VCC) a
valid trigger is recognized, which turns on comparator C1
and Nchannel transistor N11. At the same time the output
latch is set. With transistor N1 on, the capacitor CEXT rap-
idly discharges toward GND until VREF1 is reached. At this
point the output of comparator C1 changes state and tran-
sistor N1 turns off. Comparator C1 then turns off while at
the same time comparator C2 turns on. With transistor N1
off, the capacitor CEXT begins to charge through the timing
resistor, REXT, toward VCC. When the voltage across CEXT
equals VREF2, comparator C2 changes state causing the
output latch to reset (Q goes LOW) while at the same time
disabling comparator C2. This ends the timing cycle with
the monostable in the quiescent state, waiting for the next
trigger.
A valid trigger is also recognized when trigger input B goes
from GND to VCC (while input A is at GND and input clear
is at VCC2). The MM74HC123A can also be triggered when
clear goes from GND to VCC (while A is at GND and B is at
VCC6).
It should be noted that in the quiescent state CEXT is fully
charged to VCC causing the current through resistor REXT
to be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the MM74HC123A is that the output latch is set
via the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of
the value of CEXT, REXT, or the duty cycle of the input
waveform.
RETRIGGER OPERATION
The MM74HC123A is retriggered if a valid trigger occurs 3
followed by another trigger 4 before the Q output has
returned to the quiescent (zero) state. Any retrigger, after
the timing node voltage at the R/CEXT pin has begun to rise
from VREF1, but has not yet reached VREF2, will cause an
increase in output pulse width T. When a valid retrigger is
initiated 4, the voltage at the R/CEXT pin will again drop to
VREF1 before progressing along the RC charging curve
toward VCC. The Q output will remain HIGH until time T,
after the last valid retrigger.
Because the trigger-control circuit flip-flop resets shortly
after CX has discharged to the reference voltage of the
lower reference circuit, the minimum retrigger time, trr is a
function of internal propagation delays and the discharge
time of CX:
Another removal/retrigger time occurs when a short clear
pulse is used. Upon receipt of a clear, the one shot must
charge the capacitor up to the upper trip point before the
one shot is ready to receive the next trigger. This time is
dependent on the capacitor used and is approximately:
5 www.fairchildsemi.com
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