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PDF MM74C90N Data sheet ( Hoja de datos )
| Número de pieza | MM74C90N | |
| Descripción | 4-Bit Decade Counter 4-Bit Binary Counter | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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October 1987
Revised January 1999
MM74C90 • MM74C93
4-Bit Decade Counter • 4-Bit Binary Counter
General Description
The MM74C90 decade counter and the MM74C93 binary
counter and complementary MOS (CMOS) integrated cir-
cuits constructed with N- and P-channel enhancement
mode transistors. The 4-bit decade counter can reset to
zero or preset to nine by applying appropriate logic level on
the R01, R02, R91 and R92 inputs. Also, a separate flip-flop
on the A-bit enables the user to operate it as a divide-by-2,
5 or 10 frequency counter. The 4-bit binary counter can be
reset to zero by applying high logic level on inputs R01 and
R02, and a separate flip-flop on the A-bit enables the user
to operate it as a divide-by-2, -8, or -16 divider. Counting
occurs on the negative going edge of the input pulse.
All inputs are protected against static discharge damage.
Features
s Wide supply voltage range: 3V to 15V
s Guaranteed noise margin: 1V
s High noise immunity: 0.45 VCC (typ.)
s Low power compatibility:
Fan out of 2 TTL driving 74L
s The MM74C93 follows the MM74L93 Pinout
Ordering Code:
Order Number
MM74C90N
MM74C93N
Package Number
N14A
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Connection Diagrams
MM74C90
Pin Assignments for DIP
MM74C93
Top View
Top View
© 1999 Fairchild Semiconductor Corporation DS005889.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
Propagation Delay Time
from AIN to QA
Propagation Delay Time from
AIN to QB (MM74C93)
Propagation Delay Time from
AIN to QB (MM74C90)
Propagation Delay Time
from AIN to QC (MM74C93)
Propagation Delay Time from
AIN to QC (MM74C93)
Propagation Delay Time from
AIN to QD (MM74C93)
Propagation Delay Time from
AIN to QD (MM74C90)
Propagation Delay Time from
R01 or R02 to QA, QB, QC or QD
(MM74C93)
VCC = 5V
VCC = 10
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
200 400
80 150
450 850
160 300
450 800
160 300
500 1050
200 400
500 1000
200 400
600 1200
250 500
450 800
160 300
150 300
75 150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tpd0, tpd1
Propagation Delay Time from
R01 or R02 to QA, QB, QC or QD
(MM74C90)
VCC = 5V
VCC = 10V
200 400
75 150
ns
ns
tpd0, tpd1
Propagation Delay Time from
R91 or R92 to QA or QD
(MM74C90)
VCC = 5V
VCC = 10V
250 500
100 200
ns
ns
tPW Min. R01 or R02 Pulse Width
VCC = 5V
(MM74C93)
VCC = 10V
tPW Min. R01 or R02 Pulse Width
VCC = 5V
(MM74C90)
VCC = 10V
tPW Min. R91 or R92 Pulse Width
VCC = 5V
(MM74C90)
VCC = 10V
tr, tf Maximum Clock Rise
VCC = 10V
and Fall Time
VCC = 10V
tW Minimum Clock Pulse Width
VCC = 5V
VCC = 10V
fMAX
Maximum Clock Frequency
VCC = 5V
VCC = 10V
CIN Input Capacitance
Any Input (Note 3)
CPD Power Dissipation Capacitance
Per Package (Note 4)
Note 2: AC Parameters are guaranteed by DC correlated testing.
600 250
30 125
600 250
300 125
500 200
250 100
250 100
100 50
2
5
5
45
ns
ns
ns
ns
ns
ns
15 µs
5 µs
ns
ns
MHz
MHz
pF
pF
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load ac power consumption of any CMOS device. For complete explanation see Family Characteristics application note—
AN-90.
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet MM74C90N.PDF ] | |
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