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PDF MM74C374M Data sheet ( Hoja de datos )
| Número de pieza | MM74C374M | |
| Descripción | 3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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October 1987
Revised January 1999
MM74C373 • MM74C374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The MM74C373 and MM74C374 are integrated, comple-
mentary MOS (CMOS), 8-bit storage elements with 3-
STATE outputs. These outputs have been specially
designed to drive high capacitive loads, such as one might
find when driving a bus, and to have a fan out of 1 when
driving standard TTL. When a high logic level is applied to
the OUTPUT DISABLE input, all outputs go to a high
impedance state, regardless of what signals are present at
the other inputs and the state of the storage elements.
The MM74C373 is an 8-bit latch. When LATCH ENABLE is
high, the Q outputs will follow the D inputs. When LATCH
ENABLE goes low, data at the D inputs, which meets the
set-up and hold time requirements, will be retained at the
outputs until LATCH ENABLE returns high again.
The MM74C374 is an 8-bit, D-type, positive-edge triggered
flip-flop. Data at the D inputs, meeting the set-up and hold
time requirements, is transferred to the Q outputs on posi-
tive-going transitions of the CLOCK input.
Both the MM74C373 and the MM74C374 are being assem-
bled in 20-pin dual-in-line packages with 0.300” pin cen-
ters.
Features
s Wide supply voltage range: 3V to 15V
s High noise immunity: 0.45 VCC (typ.)
s Low power consumption
s TTL compatibility:
Fan out of 1driving standard TTL
s Bus driving capability
s 3-STATE outputs
s Eight storage elements in one package
s Single CLOCK/LATCH ENABLE and OUTPUT DIS-
ABLE control inputs
s 20-pin dual-in-line package with 0.300” centers takes
half the board space of a 24-pin package
Ordering Code:
Order Number Package Number
Package Description
MM74C373M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74C373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C374M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74C374N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS005906.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 3)
MM74C373, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd0, tpd1
Propagation Delay,
LATCH ENABLE to Output
VCC = 5V, CL = 50 pF
VCC = 10V, CL = 50 pF
165 330
70 140
ns
ns
tpd0, tpd1
Propagation Delay Data
In to Output
tSET-UP
Minimum Set-Up Time Data In
to CLOCK/LATCH ENABLE
VCC = 5V, CL = 150 pF
VCC = 10V, CL = 150 pF
LATCH ENABLE = VCC
VCC = 5V, CL = 50 pF
VCC = 10V, CL = 50 pF
VCC = 5V, CL = 150 pF
VCC = 10V, CL = 150 pF
tHOLD = 0 ns
VCC = 5V
195 390
85 170
155 310
70 140
185 370
85 170
70 140
ns
ns
ns
ns
ns
ns
ns
fMAX
Maximum LATCH ENABLE
VCC = 10V
35 70 ns
tPWH
Frequency
Minimum LATCH ENABLE
VCC = 5V
VCC = 10V
VCC 5V
3.5 6.7
MHz
4.5 9.0
MHz
75 150 ns
Pulse Width
tr, tf Maximum LATCH ENABLE
VCC = 10V
VCC = 5V
55 110 ns
NA µs
t1H, t0H
tH1, tH0
tTHL, tTLH
Rise and Fall Time
Propagation Delay OUTPUT
DISABLE to High Impedance
State (from a Logic Level)
Propagation Delay OUTPUT
DISABLE to Logic Level
(from High Impedance State)
Transition Time
CLE Input Capacitance
VCC = 10V
RL = 10k, CL = 5 pF
VCC = 5V
VCC = 10V
RL = 10k, CL = 50 pF
VCC = 5V
VCC = 10V
VCC = 5V, CL = 50 pF
VCC = 10V, CL = 50 pF
VCC = 5V, CL = 150 pF
VCC = 10V, CL = 150 pF
LE Input (Note 4)
NA
105 210
60 120
105 210
45 90
65 130
35 70
110 220
70 140
7.5 10
µs
ns
ns
ns
ns
ns
ns
ns
ns
pF
COD
Input Capacitance
OUTPUT DISABLE
Input (Note 4)
7.5 10 pF
CIN
COUT
Input Capacitance
Output Capacitance
Any Other Input (Note 4)
High Impedance
State (Note 4)
5 7.5 pF
10 15 pF
CPD Power Dissipation Capacitance
Per Package (Note 5)
Note 3: AC Parameters are guaranteed by DC correlated testing.
200 pF
Note 4: Capacitance is guaranteed by periodic testing.
Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note
AN-90.
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assumeany responsibility for use of any circuitry described, nocircuit patent licenses are impliedandFairchildreserves theright at any timewithout noticetochange saidcircuitry andspecifications.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MM74C374M.PDF ] | |
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