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PDF MLP1N06 Data sheet ( Hoja de datos )

Número de pieza MLP1N06
Descripción VOLTAGE CLAMPED CURRENT LIMITING MOSFET
Fabricantes Motorola Semiconductors 
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
SMARTDISCRETES
Internally Clamped, Current Limited
N–Channel Logic Level Power MOSFET
These SMARTDISCRETES devices feature current limiting for short circuit
protection, an integral gate–to–source clamp for ESD protection and gate–to–drain
clamp for over–voltage protection. No additional gate series resistance is required
when interfacing to the output of a MCU, but a 40 kgate pulldown resistor is
recommended to avoid a floating gate condition.
The internal gate–to–source and gate–to–drain clamps allow the devices to be
applied without use of external transient suppression components. The gate–to–
source clamp protects the MOSFET input from electrostatic gate voltage stresses
up to 2.0 kV. The gate–to–drain clamp protects the MOSFET drain from drain
avalanche stresses that occur with inductive loads. This unique design provides
voltage clamping that is essentially independent of operating temperature.
The MLP1N06CL is fabricated using Motorola’s SMARTDISCRETES technolo-
gy which combines the advantages of a power MOSFET output device with
on–chip protective circuitry. This approach offers an economical means for
providing additional functions that protect a power MOSFET in harsh automotive
and industrial environments. SMARTDISCRETES devices are specified over a
wide temperature range from –50°C to 150°C.
Temperature Compensated Gate–to–Drain Clamp Limits Voltage Stress
Applied to the Device and Protects the Load From Overvoltage
Integrated ESD Diode Protection
Controlled Switching Minimizes RFI
Low Threshold Voltage Enables Interfacing Power Loads to Microprocessors
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Drain Current — Continuous
Drain Current — Single Pulse
Total Power Dissipation
Electrostatic Discharge Voltage (Human Body Model)
VDSS
VDGR
VGS
ID
IDM
PD
ESD
Clamped
Clamped
±10
Self–limited
1.8
40
2.0
Operating and Storage Junction Temperature Range
THERMAL CHARACTERISTICS
TJ, Tstg
–50 to 150
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Maximum Lead Temperature for Soldering Purposes,
1/8from case
RθJC
RθJA
TL
3.12
62.5
260
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS
Single Pulse Drain–to–Source Avalanche Energy
(Starting TJ = 25°C, ID = 2.0 A, L = 40 mH) (Figure 6)
EAS
80
SMARTDISCRETES is a trademark of Motorola, Inc.
Unit
Vdc
Vdc
Vdc
Adc
Watts
kV
°C
°C/W
°C
mJ
Order this document
by MLP1N06CL/D
MLP1N06CL
Motorola Preferred Device
VOLTAGE CLAMPED
CURRENT LIMITING
MOSFET
62 VOLTS (CLAMPED)
RDS(on) = 0.75 OHMS
D
R1
G
R2
S
G
D
S
CASE 221A–06, Style 5
TO–220AB
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
©MMoottoororolal,aInTc.M19O9S6 Power MOSFET Transistor Device Data
1

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MLP1N06 pdf
1.0
0.7 D = 0.5
0.5
0.3 0.2
0.2
0.1
0.1 0.05
0.07 0.02
0.05
0.03
0.02
0.01
0.01
0.01
SINGLE PULSE
0.02 0.03 0.05 0.1
MLP1N06CL
RθJC(t) = r(t) RθJC
RθJC(t) = 3.12°C/W Max
D Curves Apply for Power
Pulse Train Shown
RTeJa(pdkT) i–mTeCat=t1P(pk) RθJC(t)
P(pk)
0.2 0.3 0.5
1.0 2.0 3.0 5.0
t, TIME (ms)
10
20 30 50
t1 t2
DUTY CYCLE, D =t1/t2
100 200 300 500
1000
Figure 9. Thermal Response (MLP1N06CL)
PULSE GENERATOR
Rgen
50
VDD
RL Vout
Vin
z = 50
DUT
50
td(on)
ton
tr
90%
td(off)
OUTPUT, Vout
INVERTED
10%
INPUT, Vin
50%
10%
PULSE WIDTH
toff
tf
90%
90%
50%
Figure 10. Switching Test Circuit
Figure 11. Switching Waveforms
ACTIVE CLAMPING
SMARTDISCRETES technology can provide on–chip real-
ization of the popular gate–to–source and gate–to–drain
Zener diode clamp elements. Until recently, such features
have been implemented only with discrete components
which consume board space and add system cost. The
SMARTDISCRETES technology approach economically
melds these features and the power chip with only a slight
increase in chip area.
In practice, back–to–back diode elements are formed in a
polysilicon region monolithicly integrated with, but electrically
isolated from, the main device structure. Each back–to–back
diode element provides a temperature compensated voltage
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free
from direct interaction with the conduction regions of the
power device, thus eliminating parasitic electrical effects
while maintaining excellent thermal coupling.
To achieve high gate–to–drain clamp voltages, several
voltage elements are strung together; the MLP1N06CL uses
8 such elements. Customarily, two voltage elements are
used to provide a 14.4 volt gate–to–source voltage clamp.
For the MLP1N06CL, the integrated gate–to–source voltage
elements provide greater than 2.0 kV electrostatic voltage
protection.
The avalanche voltage of the gate–to–drain voltage clamp
is set less than that of the power MOSFET device. As soon
as the drain–to–source voltage exceeds this avalanche volt-
age, the resulting gate–to–drain Zener current builds a gate
voltage across the gate–to–source impedance, turning on
the power device which then conducts the current. Since vir-
tually all of the current is carried by the power device, the
gate–to–drain voltage clamp element may be small in size.
This technique of establishing a temperature compensated
drain–to–source sustaining voltage (Figure 7) effectively re-
moves the possibility of drain–to–source avalanche in the
power device.
The gate–to–drain voltage clamp technique is particularly
useful for snubbing loads where the inductive energy would
otherwise avalanche the power device. An improvement in
ruggedness of at least four times has been observed when
inductive energy is dissipated in the gate–to–drain clamped
conduction mode rather than in the more stressful gate–to–
source avalanche mode.
Motorola TMOS Power MOSFET Transistor Device Data
5

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