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PDF ML6652EH Data sheet ( Hoja de datos )
| Número de pieza | ML6652EH | |
| Descripción | 10/100Mbps Ethernet Fiber and Copper Media Converter with Auto Negotiation | |
| Fabricantes | Micro Linear | |
| Logotipo |  |
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ML6652
10/100Mbps Ethernet Fiber and Copper
Media Converter with Auto Negotiation
GENERAL DESCRIPTION
FEATURES
The ML6652 is a low cost/low LED current drive single
chip Media Converter that provides 10Mbps and 100Mbps
signal conversion between twisted pair and fiber optic
Ethernet technologies. The device supports conversion
between:
10Base-T and 10Base-FL
100Base-TX and 100Base-FX/SX
100Base-FX and 100Base-SX
FLP Bursts and FLNP Bursts
The device supports 10Mbps and 100Mbps operating data
rates with Auto Negotiation using 850nm or 1300nm
optics. One or both of the fiber optic and twisted pair
interfaces can be interfaced to industry standard miniature
fiber optic components or Physical Media Dependent
(PMD) modules using Positive Emitter Coupled Logic/Low
Voltage Positive Emitter Coupled Logic (PECL/LVPECL)
compatible modes. Other wavelengths possible via
PECL/LVPECL interface.
• Complete implementation of fiber optic and twisted
pair media interface
• Intended to support ISO/IEC 8802.3, IEEE 802.3 and
TIA/EIA-785 Industry Standards, including full auto-
negotiation for twisted pair and fiber optic media
• 850nm, 1300nm miniature fiber optic components and
PMD modules
• Supports 1:1 receiver/transmitter transformer ratio for
twisted pair
• Low latency 10Mbps path
• Integrated voltage and current references
• Integrated twisted pair output wave shaping eliminates
external filtering
• Integrated twisted pair 10Base-T input filter and
100Base-TX equalizer with baseline wander correction
circuit
• Serial Management Interface
• Full and Half Duplex with Auto-Negotiation
• Integrated LED Driver
• Integrated Data Quantizer
• Small 44-Pin TQFP
• Low 3.3V operation
APPLICATIONS
• Single/Multi Port 10/100 Auto Negotiating Media
Converters
• Single/Multi Port 100Base-FX/SX to 100Base-TX Media
Converters
• Single/Multi Mode Fiber Converters
• Fiber Optic Front-End for Network Interface Cards
(NICs), Repeaters, Bridges, Hubs, Switches, and
Routers
• Residential Connectivity and Gateway/Demarcation
Products
• Redundant Link Converters
• Wavelength Converters
January 2002 Preliminary Datasheet
1 page  
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
6 AD10
I Sets the value of the PHY address bits 1 and 0 for accessing the Serial
Management Interface.
Note: this pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
Pin Name
Input Level
0
1/3 of VCC
2/3 of VCC
VCC
AD4LIW
LIW Function PHYAD4 Bit
Disabled
0
Enabled
0
Enabled
1
Disabled
1
AD32
PHYAD3 Bit
PHYAD2 Bit
00
10
11
0
Table 1.
1
AD10
PHYAD1 Bit
PHYAD0 Bit
00
10
11
01
7 PECLTP
I The copper interface is selected as shown in Table 2. When twisted pair
interface is selected, the scrambler and descrambler are enabled by default
and can be disabled with a management register bit.
When using twisted pair interface, this pin also defines the maximum
supported link distance. When the 10 meters maximum link length is selected,
the input is not equalized before being sliced.
Note: this pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
PECLTP
0
Interfaces at
TPINP/TPINN and
TPOUTP/TPOUTN
Twisted Pair
1/3 of VCC
2/3 of VCC
VCC
PECL/LVPECL
Twisted Pair
Twisted Pair
PECLTP
<30.3>
Default
0
1
0
0
Copper Length
100Base-TX
Standard
PCB Traces
PCB Traces
10m
SHORTTP
<30.2>
Default
0
0
1
1
Output Current
LOWITPOUT
<30.4>
Default
Standard
0
NA
Low
Standard
0
1
0
Table 2.
January 2002 Preliminary Datasheet
5
5 Page 
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
29 SDFO
I
BACKUP LINK FUNCTION
40 BCKPLINK
I/O
LED STATUS
41 TPINSPD
O
The two operating modes available for this pin are selected with the
configuration pin PECLQU or the configuration bit PECLQU <30.2>
Fiber Optic Interface Mode:
This pin is not used and should be connected to VCC.
PECL/LVPECL Compatible Interface Mode:
This input pin is connected to the Signal Detect (SD) output of a fiber optic
PMD. The voltage level at this pin is compared to the voltage level at pin
SDTH to determine the logic value. If it is lower than the input at FOINP/
FOINN is rejected. If it is higher than the input at FOINP/FOINN is passed to
the internal circuits.
INPUT MODE:
At power up, pin 40 (BCKPLINK) is read and the BCKPDIS register <28.1> is set
appropriately. A high (VCC) at power up causes Register 28, Bit 1 (BCKPDIS)
to be set high (1) disabling the Back-up link function. BCKPDIS can
subsequently be over written by the management interface at any time.
Note: This pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power, improper results may occur.
For BCKPLINK, use VCCD (pin 19) as the pull up point, do not add decoupling
capacitors to Pin 40 (without thoroughly understanding your PCB layout power
up dynamics the safest course is to make short connections and do not add
decoupling capacitors to this pin).
OUTPUT MODE:
After power-up, BCKPLINK is used as an output. It is Active high to enable a
secondary fiber link via a second ML6652 device (see Functional Description,
Backup Link Mode in this data sheet for details).
Use this function in forced 100Mbps mode, non loopback only
This output goes high to indicate that a 100Mbps signal is present at the TPINP/
TPINN interface, and it goes low to indicate that a 10Mbps signal is present at
the TPINP/TPINN interface. The signal can be idle or packets. This pin is set to
high impedance otherwise.
42 FOINSPD
O This output goes high to indicate that a 100Mbps signal is present at the
FOINP/FOINN interface, and it goes low to indicate that a 10Mbps signal is
present at the FOINP/FOINN interface. The signal can be idle or packets. This
pin is set to high impedance otherwise.
43 TPANDT
O When TPINSPD is in the high impedance state, no 10 or 100Mbps signal at
TPINP/TPINN, the TPANDT LED pulls low while receiving Auto-Negotiation
signal at the TPINP/TPINN interface. When TPINSPD is not in the high
impedance state, the TPANDT pin pulls low to indicate that a data packet is
being detected at the TPINP/TPINN interface. When a data packet is indicated,
the pulse width at TPANDT is stretched to a minimum of 1.3 to 2.7ms to
improve visibility. This low current LED driver interface requires a 10KΩ pull-
up resistor and a small CMOS buffer as shown in Figure 2. In any other case
this pin is in high impedance state.
VCCD
VCCD
TPAN_DT
LED
Figure 2.
10KΩ
560Ω
TPAN_DT 43
CMOS Buffer, Fairchild NC7WZ16 or Equivalent,
Buffer VCC=VCCD, Buffer Ground = DGND
January 2002 Preliminary Datasheet
11
11 Page | ||
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| PDF Descargar | [ Datasheet ML6652EH.PDF ] | |
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