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PDF ML65T541CK Data sheet ( Hoja de datos )
| Número de pieza | ML65T541CK | |
| Descripción | 3.3V High Speed Octal Buffer/Line Driver | |
| Fabricantes | Micro Linear | |
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May 1997
ML65T541*
3.3V High Speed Octal Buffer/Line Driver
GENERAL DESCRIPTION
The ML65T541 is a non-inverting octal buffer/line driver.
The high operating frequency (66MHz driving a 50pF
load) and low propagation delay (2ns) make it ideal for
very high speed applications such as processor bus
buffering cache/main memory control.
The ML65T541 uses a unique analog implementation to
eliminate the delays inherent in traditional digital designs.
Schottky clamps reduce undershoot and overshoot, and
special output driver circuits limit ground bounce. The
ML65T541 conforms to the pinout and functionality of the
industry standard FCT541 and is intended for applications
where propagation delay is critical to the system design.
FEATURES
s Low propagation delay — 2.0ns
s Fast 8-bit buffer/line driver with three-state
capability on the output
s Schottky diode clamps on all inputs to handle
undershoot and overshoot
s Onboard schottky diodes minimize noise
s Ground bounce controlled outputs
s Industry standard FCT541 type pinout
s Applications include high speed cache memory, main
memory, processor bus buffering, and graphics cards
BLOCK DIAGRAM
*Some Packages Are Obsolete
OE1 1
OE2 19
VCC
20
VCC
A0 A1 A2
234
A3 A4 A5 A6 A7
56 7 8 9
10 18 17 16
GND
B0
B1
B2
15 14 13 12 11
B3 B4 B5 B6 B7
*Some packages are obsolete
1 page  
FUNCTIONAL DESCRIPTION
The ML65T541 is a very high speed non-inverting buffer/
line driver with three-state outputs which is ideally suited
for bus-oriented applications. It provides a low propagation
delay by using an analog design approach (a high speed
unity gain buffer), as compared to conventional digital
approaches. The ML65T541 follows the pinout and
functionality of the industry standard FCT541 series of
buffers/line drivers and is intended to replace them in
designs where the propagation delay is a critical part of
the system design considerations. The ML65T541 is capable
of driving load capacitances several times larger than its
input capacitance. It is configured so that the Ai inputs go
to the Bi outputs when enabled by OE1/OE2
These unity gain analog buffers achieve low propagation
delays by having the output follow the input with a small
offset. When the output reaches one VBE off the rail, the
PMOS pull-up is activated to drive the output the rest of
the way. All inputs and outputs have Schottky clamp diodes
to handle undershoot or overshoot noise suppression in
unterminated applications. All outputs have ground
bounce suppression (typically < 400mV), high drive
output capability with almost immediate response to the
input signal, and low output skew.
The IOL current drive capability of a buffer/line driver is
often interpreted as a measure of its ability to sink current
in a dynamic sense. This may be true for CMOS buffer/
line drivers, but it is not true for the ML65T541. This is
because their sink and source current capability depends
ML65T541
on the voltage difference between the output and the input.
The ML65T541 can sink or source more than 100mA to a
load when the load is switching due to the fact that during
the transition, the difference between the input and output
is large. IOL is only significant as a DC specification, and
is 5mA.
ARCHITECTURAL DESCRIPTION
Until now, buffer/line drivers have been implemented in
CMOS logic and made to be TTL compatible by sizing the
input devices appropriately. In order to buffer large
capacitances with CMOS logic, it is necessary to cascade
an even number of inverters, each successive inverter
larger than the preceding, eventually leading to an inverter
that will drive the required load capacitance at the required
frequency. Each inverter stage represents an additional
delay in the gating process because in order for a single
gate to switch, the input must slew more than half of the
supply voltage. The best of these CMOS buffers has
managed to drive a 50pF load capacitance with a delay of
3.2ns. Micro Linear has produced a dual quad buffer/line
driver with a delay of less than 2ns by using a unique
circuit architecture that does not require cascaded logic
gates. The ML65T541 uses a feedback technique to
produce an output that follows the input. If the output
voltage is not close to the input, then the feedback
circuitry will source or sink enough current to the load
capacitance to correct the discrepancy.
The basic architecture of the ML65T541 is shown in
Figure 5. It is implemented on a 1.5µm BiCMOS process.
R8
Q1
INV
R1
IN
VCC
Q2 M1
R3 R4
Q4
Q3 Q5
R5
R2
Q6
R6
R7
Q7
GND
Figure 5. One buffer cell of the ML65T541
OUT
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ML65T541CK.PDF ] | |
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