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PDF ML4903 Data sheet ( Hoja de datos )
| Número de pieza | ML4903 | |
| Descripción | High Current Synchronous Buck Controller | |
| Fabricantes | Micro Linear | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML4903 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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July 1999
ML4903
High Current Synchronous Buck Controller
GENERAL DESCRIPTION
The ML4903 high current synchronous buck controller
provides high efficiency DC/DC conversion to generate
VCCP for processors such as the Pentium® Pro and Pentium
II from Intel®.
The ML4903 controller, when combined with two external
MOSFETs, generates output voltages between 1.8V and
3.5V from a 12V supply. The output voltage is selected via
an internal 2 chord 4-bit DAC. In the upper range, the
output can be set between 2.1V and 3.5V in 100mV steps.
In the lower range, the output can be set between 1.8V
and 2.05V in 50mV steps. Output currents in excess of
20A can be attained at efficiencies greater than 80%.
The ML4903 can be enabled/disabled via the SHDN pin.
While disabled, the output of the regulator is completely
isolated from the circuit’s input supply. The ML4903
employs fixed-frequency PWM control combined with a
sophisticated control loop enhancement circuit to provide
excellent load transient response.
FEATURES
s Designed to meet Pentium Pro and Pentium II VRM
power supply requirements
s DC regulation to +1% maximum
s Proprietary circuitry provides transient response of ±5%
maximum over a 0A to 14A load range
s Programmable output voltage (1.8V to 3.5V) is set by
an onboard 2 chord 4-bit DAC
s Synchronous buck topology for maximum power
conversion efficiency
s Fixed frequency operation for easier system integration
s Integrated anti-shootthrough logic, short circuit
protection, shutdown, and UV lockout
BLOCK DIAGRAM
VDD
19
VCC
18
10.5V
4.4V
+
–
+
–
UVLO
5V
30µA
PROTECT
20
3.5V
+
–
SHDN
6
D0
1
D1
2
D2
3
D3
4
RANGE
5
2 CHORD
4 BIT DAC
VDAC
VDAC + 3%
VFB
VDAC - 3%
+
–
+
–
CONTROL
LOGIC
+
–
200kHz
VDAC + 10%
VDAC + 3%
VFB
VDAC - 10%
VDAC - 3%
+
–
+
–
P DRV
17
N DRV
16
PWR GND
15
COMP
13
VFB
– 11
+ VDAC
+ -107mV ISENSE
– 12
PWR GOOD
8
3.5V
REFERENCE
VREF
9
GND
10
1
1 page  
FUNCTIONAL DESCRIPTION
The ML4903 PWM controller permits the construction of a
simple yet sophisticated power supply for Intel’s Pentium
Pro and Pentium II microprocessor families. The ML4903
and its associated circuitry can be built either as a
Voltage Regulator Module (VRM) or as a dedicated supply
on the motherboard. The ML4903 controls a P-channel
MOSFET and an N-channel MOSFET in a synchronous
buck regulator topology to convert a 5V input to the
voltage required by the microprocessor. The output
voltage can be set between 1.8V and 3.5V, as selected by
an onboard DAC. Other features which facilitate the
design of DC-DC converters for any type of processor
include a trimmed 1% reference, special transient-
response optimization in the feedback paths, a shutdown
input, input and output power good monitors, and
overcurrent protection.
OUTPUT VOLTAGE SELECTION
The inputs of the internal 2-chord 4-bit DAC come from
open collector signals provided by the processor. These
signals specify what supply voltage the microprocessor
requires. The output voltage of the buck converter is
compared directly with the DAC voltage to maintain
regulation. D3 is the MSB input and D0 is the LSB input
of the DAC, while RANGE selects the output voltage
range and the LSB voltage increment of the DAC. The
output of the DAC is between 2.121V to 3.535V in 100mV
steps when RANGE = 1, and between 1.818V to 2.071V in
50mV steps when RANGE = 0. The output voltage set by
the DAC is 1% above the processor’s nominal operating
voltage to counteract the effects of connector and PC
trace resistance, and of the instantaneous output voltage
droop which occurs when a transient load is applied. For
codes 00110 to 01111 and code 11111, the P DRV and N
DRV outputs are disabled.
VOLTAGE FEEDBACK LOOP
The ML4903 contains two control loops to improve the
load transient response. The output voltage is directly
monitored via the VFB pin and compared to the desired
output voltage set by the internal DAC. When the output
voltage is within +3% of the DAC voltage, the
proportional control loop (closed by the voltage error
amplifier) keeps the output voltage at the correct value. If
the output falls below the DAC voltage by more than 3%,
one side of the transient loop is activated, forcing the
output of the ML4903 to maximum duty cycle until the
output comes back within the +3% limit. If the output
voltage rises above the DAC voltage by more than 3%,
the other side of the transient loop is activated, and the P-
channel MOSFET drive is disabled until the output comes
back within the +3% limit. If the output voltage rises
above the DAC voltage by more than 10%, both P DRV
and N DRV will be disabled to turn the converter off.
During start-up, the transient loop is disabled until the
output voltage is within -3% of the DAC voltage.
ML4903
POWER GOOD (PWR GOOD)
An open drain signal is provided by the ML4903 which
tells the microprocessor when the entire power system is
functioning within the expected limits. PWR GOOD will
be false (low) if either the 5V or 12V supply is not in
regulation, when the SHDN pin is pulled low, or when the
output is not within +10% of the nominal output voltage
selected by the internal DAC.
When PWR GOOD is false, the PWR GOOD voltage
window is held to +3%; when PWR GOOD is true (high),
the window is expanded to +10%. Using different
windows for coming into and going out of regulation
makes sure that PWR GOOD does not oscillate during the
start-up of the microprocessor.
INTERNAL REFERENCE
The ML4903 contains a 3.535V, temperature
compensated, precision band-gap reference. The VREF pin
is connected to the output of this reference, and should be
bypassed with a 100nF to 220nF ceramic capacitor for
proper operation.
OVERCURRENT PROTECTION
Overcurrent sensing for the ML4903 application circuit is
typically accomplished by monitoring the voltage drop
across the synchronous rectifier MOSFETs (Q3||Q4) during
their conduction period. Alternately, current can be
sensed using a low-value, low-inductance sense resistor
connected between the most negative end of the current
recirculating element and ground. In either case, the
resulting IR drop is presented to the ML4903’s internal
overcurrent comparator via the part’s ISENSE pin. The
overcurrent comparator has approximately 250ns of
leading-edge blanking. This blanking interval allows the
ML4903 to ignore spurious circuit voltages such as
inductive transients and the synchronous rectifier’s drain-
body diode voltage during the anti-shootthrough interval.
Following this blanking interval, the comparator will turn
on if the voltage on the ISENSE pin is more negative than
–80mV.
Each time the overcurrent comparator turns on, the
PROTECT pin of the ML4903 sources a small current
(30µA) into an external RC network. If this current source
is activated over a number of cycles, the voltage on the
PROTECT pin will charge above 3.5V, signaling a
sustained overcurrent or short circuit at the load. This will
cause the P DRV output to turn off. P DRV will remain off
until the capacitor attached to the PROTECT pin has
discharged down to 1.5V, at which time the converter is
re-enabled. If the fault causing the overcurrent condition
has not been cleared, the overcurrent protection cycle
will repeat, and the ML4903 circuit will operate in a
“hiccup” mode to protect itself, the input supply, and the
output.
5
5 Page 
DESIGN CONSIDERATIONS (Continued)
of the ML4903, and the VDD bypass capacitors C10 and
C15 serve this purpose. The VDD bypass capacitors should
be returned to PWR GND or to the PC board ground
plane. They should not be returned to GND due to high
transient currents which could interfere with the current
sensing function.
VCC is the input to the 5V undervoltage lockout
comparator circuitry. The 5V UVLO function makes the
start-up of the ML4903 independent of power sequencing.
It also provides load protection in case VCC should go
below acceptable levels. To reject logic switching noise
on the 5V input, an RC filter should be used between the
15kVWs,oaunrcdeCa1n1d=V2C2C0. nTyf.pical values for this filter are R2 =
ML4903
Optional capacitor C16 may be needed in some layouts
to filter out “glitches” which could occur on the PWR
GOOD signal. In conjunction with the resistive pullup for
the PWR GOOD line, its value should yield an RC
product of approximately 5µs.
Power MOSFETs in 8-pin SOIC packages are among the
best for this application, especially for the P-channel
devices. Using P-channel MOSFETs minimizes
component count while ensuring full enhancement of
both the P-channel and N-channel MOSFETs. If 8-pin
SOIC MOSFETs are chosen, keep in mind that the
thermal dissipation capability of these parts is largely
dictated by the copper area available to their drains. A
good layout will maximize this area.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ML4903.PDF ] | |
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