|
|
PDF ML4826IS-2 Data sheet ( Hoja de datos )
| Número de pieza | ML4826IS-2 | |
| Descripción | PFC and Dual Output PWM Controller Combo | |
| Fabricantes | Micro Linear | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ML4826IS-2 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
June 1997
ML4826*
PFC and Dual Output PWM Controller Combo
GENERAL DESCRIPTION
FEATURES
The ML4826 is a high power controller for power factor
corrected, switched mode power supplies. PFC allows the
use of smaller, lower cost bulk capacitors, reduces power
line loading and stress on the switching FETs, and results
in a power supply that fully complies with IEC1000-3-2
specifications. The ML4826 includes circuits for the
implementation of a leading edge, average current “boost”
type power factor correction and a trailing edge, pulse
width modulator (PWM) with dual totem-pole outputs.
The device is available in two versions; the ML4826-1
(fPWM = fPFC) and the ML4826-2 (fPWM = 2 x fPFC).
Doubling the switching frequency of the PWM allows the
user to design with smaller output components while
maintaining the optimum operating frequency for the PFC.
An over-voltage comparator shuts down the PFC section in
the event of a sudden decrease in load. The PFC section
also includes peak current limiting and input voltage
brown-out protection. The PWM section can be operated
in current or voltage mode at up to 250kHz and includes a
duty cycle limit to prevent transformer saturation.
s Internally synchronized PFC and PWM in one IC
s Low total harmonic distortion
s Reduced ripple current in the storage capacitor
between the PFC and PWM sections
s Average current, continuous boost, leading edge PFC
s High efficiency trailing edge PWM with dual
totem-pole outputs
s Average line voltage compensation with brown-out
control
s PFC overvoltage comparator eliminates output
“runaway” due to load removal
s Current-fed multiplier for improved noise immunity
s Overvoltage protection, UVLO, and soft start
BLOCK DIAGRAM
* This Part Is End Of Life As Of August 1, 2000
20 11
VEAO
AGND
1
IEAO
POWER FACTOR CORRECTOR
VFB
19
2.5V
IAC
2
VRMS
4
ISENSE
3
RAMP 1
8
RTCT
7
VEA
-
+
3.5kΩ IEA
-
+
GAIN
MODULATOR
8V
3.5kΩ
+
-
OSCILLATOR
2.7V
-1V
RAMP 2
9
8V
x2
(-2 VERSION ONLY)
DUTY CYCLE
LIMIT
VDC
6
VCC
SS
5
50µA
8V
1.5V
-
+
-
+
VFB
2.5V
VIN OK
-
+
1V
DC ILIMIT
10
PULSE WIDTH MODULATOR
OVP
+
-
+
-
PFC ILIMIT
-
+ DC ILIMIT
VCCZ
VCCZ
13.5V
17
VCC
7.5V
REFERENCE
VREF
18
SQ
RQ
SQ
PFC OUT
15
RQ
SQ
TQ
SQ
RQ
UVLO
VCC2
16
PWM 2
14
PGND
VCC2
PWM 1
13
PGND
12
1
1 page  
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
PFC
Minimum Duty Cycle
Maximum Duty Cycle
Output Low Voltage
Output High Voltage
PWM
Rise/Fall Time
Duty Cycle Range
Output Low Voltage
Output High Voltage
SUPPLY
Rise/Fall Time
Shunt Regulator Voltage (VCCZ)
VCCZ Load Regulation
VCCZ Total Variation
Start-up Current
Operating Current
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
CONDITIONS
ML4826-1, VIEAO > 4.0V
ML4826-2, VIEAO > 5.7V
VIEAO < 1.2V
IOUT = –20mA
IOUT = –50mA
IOUT = 10mA, VCC = 8V
IOUT = 20mA
IOUT = 50mA
CL = 1000pF
IOUT = –20mA
IOUT = –50mA
IOUT = 10mA, VCC = 8V
IOUT = 20mA
IOUT = 50mA
CL = 1000pF
25mA < ICC < 55mA
Load, temp
VCC = 11.2V, CL = 0
VCC < VCCZ – 0.5V, CL = 0
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the VFB pin.
Note 3: Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5V)-1.
ML4826
MIN TYP MAX UNITS
0%
0%
90 95
%
0.4 0.8 V
0.6 3.0 V
0.7 1.5 V
9.5 10.5
V
9.0 10
V
50 ns
0-47
9.5
9.0
0-48
0.4
0.6
0.7
10.5
10
50
0-50
0.8
3.0
1.5
%
V
V
V
V
V
ns
12.8 13.5 14.2
V
±150 ±300 mV
12.4 14.6 V
0.7 1.1 mA
22 28 mA
12 13 14 V
2.65 3.0 3.35 V
5
5 Page 
FUNCTIONAL DESCRIPTION (Continued)
Volts peak. The composite waveform feeding the RAMP2
pin for the PWM consists of the reflected output current
signal along with the transformer magnetizing current and
the slope compensation signal.
Equation 8 describes the composite signal feeding
RAMP2, consisting of the primary current of the main
transformer and the slope compensation. Equation 9
solves for the required slope compensation peak voltage.
VRAMP2
=
IPRI +
1×
2
VOUT
L
× NS
NP
×
TS
×
1
nCT
≤ VFB
– 1.5V
(8)
VSC
=
21 ×
VOUT
L
× NS
NP
×
TS
×
RSENSE
nCT
=
1×
2
48V ×
20µH
14
90
× 5µ sec 471Ω
200
= 2.2V
Soft Start
(9)
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.5V. Start-up delay can be programmed
by the following equation:
CSS
=
tDELAY
×
50µA
1.5V
(10)
where CSS is the required soft start capacitance, and
tDELAY is the desired start-up delay.
ML4826
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
Solving for the minimum value of CSS:
CSS
=
5ms ×
50µA
1.5V
= 167nF
(11)
VCC
The ML4826 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the
voltage internal to the part at 13.5V. This allows a low
power dissipation while at the same time delivering 10V
of gate drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying the part.
There are a number of different ways to supply VCC to the
ML2826. The method suggested in Figure 5, is one which
keeps the ML4826 ICC current to a minimum, and allows
for a loosely regulated bootstrap winding. By feeding
external gate drive components from the base of Q1, the
constant current source does not have to account for
variations in the gate drive current. This helps to keep the
maximum ICC of the ML4826 to a minimum. Also, the
current available to charge the bootstrap capacitor from
the bootstrap winding is not limited by the constant
ISENSE
x Former
4 x IN4148
T3
200:1
Q14
2N2222
D1
C26
220pF
R16
471Ω
R21
8.63kΩ
C11
1000pF
17 VCC
18 VREF
7 RTCT
R40
47.0kΩ
RAMP2
9
1.5V
AGND
11
1V
R13
2.2kΩ
10 DC ILIMIT
R38
U2
10.0kΩ
6 VDC
PWM CMP
–
+
DC ILIMIT
–
+
Figure 4. Slope Compensation and Current Sense
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ML4826IS-2.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ML4826IS-1 | PFC and Dual Output PWM Controller Combo | Micro Linear |
| ML4826IS-2 | PFC and Dual Output PWM Controller Combo | Micro Linear |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |