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PDF ML4669IQ Data sheet ( Hoja de datos )
| Número de pieza | ML4669IQ | |
| Descripción | 10BASE-FL to 10BASE-T Converter | |
| Fabricantes | Micro Linear | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML4669IQ (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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July 2000
ML4664*/ML4669*
10BASE-FL to 10BASE-T Converter
GENERAL DESCRIPTION
The fully pin-compatible ML4664/ML4669 pair provide
conversion from 10BASE-T copper media to 10BASE-FL
fiber media in a single chip. They are compliant with
Ethernet IEEE 802.3 10BASE-T and 10BASE-FL standards.
The ML4664/69 uses a single 5V supply, and requires no
crystal or clock.
Their 10BASE-FL transmitter offers a current drive output
that directly drives a fiber optic LED transmitter. Their
receiver offers a highly stable fiber optic data quantizer
capable of accepting input signals as low as 2mVP-P with
a 55dB dynamic range.
The 10BASE-T portion of the pair contains current driven
transmitter outputs that offer superior performance
because their switching is highly symmetric, resulting in
lowered RFI noise and jitter. By changing one external
resistor the pair easily interfaces to 100W unshielded
twisted pair, 150W shielded twisted pair, or a range of
other characteristic impedances.
The ML4664 does not pass along disconnect information,
while the ML4669 does. A loss of light at the optical
inputs does not stop link pulses from being sent at the
twisted pair transmitter in the ML4664, but in the
ML4669 the link pulses stop. Also, a loss of link at the
twisted pair inputs will not stop the optical transmitter
from sending idle in the ML4664, but the ML4669 stops
sending idle.
FEATURES
s Full duplex operation
s Five network status LED outputs
s Industrial temperature option
10BASE-FL FEATURES:
s Highly stable data quantizer with 55dB input dynamic
range
s Input sensitivity as low as 2mVP-P
s Up to 100mA maximum current driven fiber optic LED
output for accurate launch power (PLCC package)
10BASE-T FEATURES:
s Current driven output for low RFI noise and low jitter
s Drives 100W unshielded or 150W shielded twisted pair
s Polarity detect status pin capable of driving an LED
s Automatic polarity correction
s On-chip link test with enable/disable option
* Some Packages Are Obsolete
BLOCK DIAGRAM
LTF
LINK PULSE
CHECK
TPLED POLDIS
IDLE
GENERATOR
RRSET
RTSETOP
TPIN
2
RX SQUELCH
TP
POLARITY
CORRECT
OP OPOUT
TX OPVCC
TPOUT
2
LINK PULSE
GENERATOR
RTSETTP
TP
TX
TxCAP0
TxCAP1
RX SQUELCH
TP
LMON
(LOW LIGHT) OPLED
THRESHOLD
GENERATOR
QUANTIZER
VDC
CTIMER
2 OPIN
1
1 page  
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.
Power Supply Voltage Range
VCC ................................................................... GND –0.3 to 6V
Input Voltage Range: Digital Inputs
(SQEN, LBDIS) ....................... GND –0.3 to VCC +0.3V
Tx+, Tx–, VIN+, VIN– .............. GND –0.3 to VCC +0.3V
Junction Temperature ............................................. 150°C
Storage Temperature ................................ –65°C to 150°C
Lead Temperature (Soldering) ................................ 260°C
ML4664/ML4669
Thermal Resistance (qJA)
PLCC ............................................................... 68°C/W
TQFP ............................................................... 80ºC/W
OPERATING CONDITIONS
Temperature Range
ML4664/ML4669CX .................................. 0°C to 70°C
ML4664/ML4669IQ ............................... –40°C to 85°C
Supply Voltage (VCC) ......................................... 5V ± 5%
LED on Current ...................................................... 10mA
RRSET ........................................................ 61.9kW ± 1%
RTSETOP ....................................................... 115W ± 1%
RTSETTP ........................................................ 220W ± 1%
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = Operating Temperature Range, VCC = OPVCC = AVCC = 5V ± 5% (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
ICC Power Supply Current
While Transmitting
RTSETOP = 115W
140
VREF Reference Voltage
C Suffix
I Suffix
2.30
2.25
2.60
2.67
VOL LED Drivers: VOL
RL = 300 for OPLED, TPLED,
POLLED LTF, and LMON
1.5
3.5
IOPOUT OP Transmit Peak Output Current
RTSETOP = 115 (Note 2) C Suffix
I Suffix
47
46
52 57
58.5
ITPOUT
VTPSQ
HTP
VTPIN
RTPIN
VOPTH
TP Transmit Peak Output Current
TP Receive Squelch Voltage
TP Receive Squelch Hysteresis
TP Receive Input Voltage
TP Receive Input Resistance
OP Receive Input Threshold
Voltage
RTSETTP = 220
VTHADJ = VREF
42
300 450 585
50
300 3100
4
567
HOP
OP Receive Input Threshold
Hysteresis
20
VOPIN
ROPIN
VOPCM
OP Receive Input Voltage
OP Receive Input Resistance
OP Receive Common Mode
Voltage
2 1600
0.8 1.3 2.0
1.65
AV
VOFF
Amplifier Gain
Input Offset
VDC = VREF (DC Loop Inactive)
100
3
VN Input Referred Noise
ITH Input Bias Current at VTHADJ
50MHz Bandwidth
VTHADJ = VREF
–200
25
0
200
UNITS
mA
V
V
V
mA
mA
mA
mVP-P
%
mVP-P
kW
mVP-P
%
mVP-P
kW
V
V/V
mV
µV
µA
5
5 Page 
SYSTEM DESCRIPTION (Continued)
TPOUTP and TPOUTN, can drive a 100W, 150W load, or
a variety of impedances that are characteristic of the
twisted pair wire. RTSETTP selects the current into the
TPOUTP, TPOUTN pins. This current along with the
characteristic impedance of the cable determines the
output voltage.
Once the characteristic impedance of the twisted pair is
determined, one must select the appropriate RTSETTP
resistor as well as match the terminating impedances of
the transmit and receive filter. The RTSETTP resistor can
be selected as follows:
WRTSETTP = RL 220
100
(2)
Where RL is the characteristic impedance of the twisted
pair cable.
The transmitter incorporates a pre-equalization circuit for
driving the twisted pair line. Pre-equalization
compensates for the amplitude and phase distortion
introduced by the twisted pair cable. The twisted pair line
will attenuate the 10MHz signal more than the 5MHz
signal. Therefore pre-equalization insures that both the 5
and 10MHz components will be roughly the same
amplitude at the far end receiver.
The pre-equalization circuit reduces the current output
when a 5MHz bit is being transmitted. After 50ns of a
5MHz bit, the current level is reduced to approximately
2/3 of its peak for the remaining 50ns. Figure 9 illustrates
the pre-equalization.
An on-chip one-shot determines the pulse width of the
pre-equalized transmit signal. This requires an external
capacitor connected to pins TxCAP0 and TxCAP1. The
proper value for this one-shot is 680pF. Pre-equalization
can be disabled by shorting TxCAP0 and TxCAP1 together.
The transmitter enters the idle state when it detects start
of idle on OPINP and OPINN input pins. The transmitter
maintains a minimum differential output voltage of at
least 450mV for 250ns after the last low to high transition.
The driver differential output voltage will then be within
50mV of 0V within 45 bit times.
OP SQUELCH
The input to the optical receiver comes from a fiber optic
pre-amp. At the start of packet reception no more than
2.7 bits are received from the fiber cable and not
transmitted onto the TP outputs. The receive squelch will
reject frequencies lower than 2.51MHz.
ML4664/ML4669
While in the unsquelch state, the receive squelch circuit
looks for the start of idle signal at the end of the packet.
Start of idle occurs when the input signal remains idle for
more than 160ns. When start of idle is detected, the
receive squelch circuit returns to the squelch state and the
start of idle signal is output on the twisted pair outputs
TPOUTP, TPOUTN.
INPUT AMPLIFIER
The OPINP, OPINN input signal is fed into a limiting
amplifier with a gain of about 100 and input resistance of
1.3kW. Maximum sensitivity is achieved through the use
of a DC restoration feedback loop and AC coupling the
input. When AC coupled, the input DC bias voltage is set
by an on-chip network at about 1.7V. These coupling
capacitors, in conjunction with the input impedance of
the amplifier, establish a high pass filter with 3dB corner
frequency, fL, at:
fL =
1
2p 1300 C
(3)
Since the amplifier has a differential input, two capacitors
of equal value are required. If the signal driving the input
is single ended, one of the coupling capacitors can be
tied to AVCC.
The internal amplifier has a lowpass filter built-in to band
limit the input signal which in turn will improve the
signal to noise ratio.
Although the input is AC coupled, the offset voltage
within the amplifier will be present at the amplifier’s
output. In order to reduce this error a DC feedback loop
is incorporated. This negative feedback loop nulls the
offset voltage, forcing VOS to be zero. Although the
capacitor on VDC is non-critical, the pole it creates can
effect the stability of the feedback loop. To avoid stability
problems, the value of this capacitor should be at least 10
times larger than the input coupling capacitors.
The comparator is a high-speed differential zero crossing
detector that slices and accurately digitizes the receive
signal. The output of the comparator is fed into the
receive squelch circuit.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ML4669IQ.PDF ] | |
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