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PDF ML4425CP Data sheet ( Hoja de datos )
| Número de pieza | ML4425CP | |
| Descripción | Sensorless BLDC Motor Controller | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML4425CP (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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ML4425
Sensorless BLDC Motor Controller
www.fairchildsemi.com
Features
• Stand-alone operation
• Motor starts and stops with power to IC
• On-board start sequence: Align ♦ Ramp ♦ Set Speed
• Patented Back-EMF commutation technique provides
jitterless torque for minimum “spin-up” time
• Onboard speed control loop
• PLL used for commutation provides noise immunity from
PWM spikes, compared to noise sensitive zero crossing
technique
• PWM control for maximum efficiency
• Direct FET drive for 12V motors; drives high voltage
motors with IC buffers
Block Diagram
FB A
22
FB B
23
FB C
24
17
VDD CAT
750nA
1.5V
–
+
BACK
EMF
SAMPLER
19
VDD
CRT
750nA
–
1.5V
+
General Description
The ML4425 PWM motor controller provides all of the
functions necessary for starting and controlling the speed of
delta or wye wound Brushless DC (BLDC) motors without
Hall Effect sensors. Back EMF voltage is sensed from the
motor windings to determine the proper commutation phase
sequence using a PLL. This patented sensing technique will
commutate a wide range of 3-Phase BLDC motors and is
insensitive to PWM noise and motor snubbing circuitry.
The ML4425 limits the motor current using a constant off-
time PWM control loop. The velocity loop is controlled with
an onboard amplifier. The ML4425 has circuitry to ensure
that there is no shoot-through in directly driven external
power MOSFETs.
The timing of the start-up sequence is determined by the
selection of three timing capacitors. This allows optimization
for a wide range of motors and loads.
21
CRR
20 15
SPEED CVCO
FB
16
RVCO
VDD
500nA
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
13
VCO
OUT
8
SPEED SET
+
–
3.9V
5
SPEED COMP
CT
6
1.7V
ISENSE
1
20kHz
1.7V
ILIMIT
12
VCO
OUT
–
+
×5
VREF
16kΩ
–
+
8kΩ
R
A
FB
EC
D
ILIMIT
1-SHOT
CIOS
26
COMMUTATION
STATE MACHINE
1.4V
VDD
–
+
4kΩ
UVLO
GATING
LOGIC
&
OUTPUT
DRIVERS
HA
2
HB
3
HC
4
LA
9
LB
10
LC
11
UV FAULT
18
REFERENCE
BRAKE
25
VDD
GND
RREF VREF
14
28 27
7
REV. 1.0.2 7/2/01
1 page  
PRODUCT SPECIFICATION
ML4425
Electrical Characteristics (continued)
Unless otherwise specified, VDD = 12V ± 10%, RSENSE = 1Ω, CVCO = 10nF, CIOS = 100pF, RREF = 137kΩ,
TA = Operating Temperature Range (Notes 1, 2).
Symbol
Parameter
Conditions
Logic Outputs (VCO/TACH, UV FAULT) (Note 3)
VCO/TACH Output High Voltage IOUT = –100µA
VCO/TACH Output Low Voltage IOUT = 400µA
UV FAULT Output High Voltage IOUT = –10µA
C Suffix
I Suffix
Min.
2.2
3.4
3.2
Typ.
4.5
UV FAULT Output Low Voltage IOUT = 400µA
Back-EMF Sampler
SPEED FB Align Mode Voltage
125
SPEED FB Ramp Mode Current
C Suffix 500
I Suffix 500
SPEED FB Run Mode Current State A, CRT = 5V,
VPHB = VDD/3
C Suffix
I Suffix
30
27
State A, CRT = 5V, VPHB = VDD/2
State A, CRT = 5V,
VPHB = 2↔VDD/3
C Suffix
I Suffix
–15
–90
–90
Output Drivers
High Side Driver Output Low
Current
High Side Driver Output High
Voltage
VHX = 2V
IHX = –10µA
0.5
VCC – 1.3
Low Side Driver Output Low
Voltage
ILX = 1mA
0.2
Low Side Driver Output High
Voltage
Phase C Cross-conduction
Lockout Threshold
V(ISENSE) = 0V
C Suffix VDD – 2.2
I Suffix VDD – 2.9
VDD – 3.0
Supply
IDD VDD Current
UVLO Threshold
C Suffix 8.8
32
9.5
I Suffix
8.6
UVLO Hysteresis
150
Notes:
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
2. For explanation of states, see Figure 4 and Table 1.
3. The BRAKE and UV FAULT pins each have an internal 4kΩ resistor to the internal reference.
Max.
0.6
5.4
5.6
0.6
250
720
750
90
90
15
–30
–27
1.2
0.7
50
10.2
10.3
Units
V
V
V
V
V
mV
nA
nA
µA
µA
µA
µA
µA
mA
V
V
V
V
V
mA
V
V
mV
REV. 1.0.2 7/2/01
5
5 Page 
PRODUCT SPECIFICATION
CAT
CRT
CRR
TO
SPEED FB
FILTER
ML4425
FB A
FB B
FB C
VDD CAT
750nA
1.5V
–
+
BACK
EMF
SAMPLER
VDD
CRT
750nA
–
1.5V
+
TO RESET INPUT
OF COMMUTATION
STATE MACHINE
CRR
SPEED CVCO
FB
RVCO
VDD
500nA
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
Figure 8. ML4425 Start-up Circuitry for Controlling the Align and Ramp Times
Run Mode (Back EMF Sensing)
At the end of ramp mode the controller goes into run mode.
In run mode, the back EMF sensing is enabled and commuta-
tion is now under the control of the phase locked loop. Motor
speed is now regulated by the speed control loop.
PWM Speed Control
Speed control is accomplished by setting a speed command
at SPEED SET with an input voltage from 0 to 6.9V (VREF).
The accuracy of the speed command is determined by the
external components RVCO and CVCO. There are a number of
methods that can be used to control the speed command of
the ML4425. One is to use a 10kΩ potentiometer from VREF
to ground with the wiper connected to SPEED SET. If
SPEED SET is controlled from a microcontroller, one of its
DACs can be used with VREF as its input reference.
The speed command is compared with the sensed speed from
SPEED FB through a transconductance error amplifier. The
output of the speed error amplifier is SPEED COMP. SPEED
COMP is clamped between one diode drop above 3.9V
(approximately 4.6V) and one diode drop below 1.7V
(approximately 1V) to prevent speed loop “wind-up”. Speed
loop compensation components are connected to this pin as
shown in Figure 9. The speed loop compensation compo-
nents are calculated as follows:
CSC
=
----------2---6---.--9-----×-----N-----×-----V----M-----O----T---O----R-----×-----C----V----C---O-----------
fSB × Ke 2.5 + 98.696 × τm2 × fSB2
RSC = 2----π-----×-----f--S-1--B-0----×-----C----S----C-
(9a)
(9b)
Where fSB is the speed loop bandwidth in Hz.
VREF
10kΩ
RSC
CSC
CT
FROM
SPEED FB
+
–
SPEED SET
3.9V
SPEED COMP
1.7V
–
+
TO
GATING
LOGIC &
OUTPUT
DRIVERS
CT
1.7V
20kHz
PWM ON/OFF
FROM ILIMIT
ONE-SHOT
Figure 9. Speed Control Loop Component Connections
The voltage on SPEED COMP is compared with a ramp
oscillator to create a PWM duty cycle. The PWM ramp oscil-
lator creates a sawtooth function from 1.7V to 3.9V as shown
in Figure 9. A negative clamp at one diode drop below 1.7V
(approximately 1V) starts the oscillator on power up. The
frequency of the ramp oscillator is set by a capacitor to
ground CIOS and is selected using the following equation:
CT = -f----P-------W--I--------M--2----.-×-4----V5---0----µ----A--
(10)
Where fPWM is the PWM frequency in Hz. The PWM duty
cycle from the speed control loop is gated the current limit
one shot that controls the LA, LB, and LC output drivers.
REV. 1.0.2 7/2/01
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ML4425CP.PDF ] | |
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