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PDF MK3727S Data sheet ( Hoja de datos )

Número de pieza MK3727S
Descripción LOW COST 24 - 36 MHZ 3.3 VOLT VCXO
Fabricantes Integrated Circuit Systems 
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MK3727
LOW COST 24 - 36 MHZ 3.3 VOLT VCXO
Description
The MK3727 series of devices include the original
MK3727S, MK3727A, and the new MK3727C and
MK3727D. The MK3727D and MK3727C are drop-in
replacements for the MK3727S and MK3727A devices.
Compared to these earlier devices the MK3727D and
MK3727C offer a wider operating frequency range and
improved power supply noise rejection. The MK3727D
is recommended for new designs.
The MK3727 series combines the functions of a VCXO
(Voltage Controlled Crystal Oscillator) and PLL (Phase
Locked Loop) frequency doubler onto a single chip.
Used in conjunction with an external pullable quartz
crystal, this monolithic integrated circuit replaces more
costly hybrid (canned) VCXO devices. The MK3727 is
designed primarily for data and clock recovery
applications within end products such as ADSL
modems, set-top box receivers, and telecom systems.
The MK3727D is recommended for new designs. The
MK3727D exhibits a moderate VCXO gain of
120ppm/V typical, when used with a high quality
external pullable quartz crystal. The MK3727C offers a
higher VCXO gain of 150ppm/V, similar to the earlier
MK3727A. The higher intrinsic VCXO gain of the
MK3727C may help compensate for the reduced
pullability of a low quality crystal used in some
applications. However, higher VCXO gain may also
increase clock output phase noise.
The frequency of the on-chip VCXO is adjusted by an
external control voltage input into pin VIN. Because
Block Diagram
VIN is a high impedance input, it can be driven directly
from an PWM RC integrator circuit. Frequency output
increases with VIN voltage input. The usable range of
VIN is 0 to 3V.
Features
MK3727D and MK3727C are drop-in upgrades to the
earlier MK3727S and MK3727A devices
MK3727D and MK3727C offer 24-36 MHz output
frequency range (output frequency = 2x crystal
frequency) and improved power supply noise
rejection
Uses an inexpensive 12 to 18 MHz external crystal
Ideal for ADSL applications using 17.664 MHz
external pullable crystal to generate locked 35.328
MHz clock physical layer clock
Ideal for set-top box applications using 13.5 MHz
external pullable crystal to generate lock 27 MHz
clock transport video clock
On-chip VCXO with guaranteed pull range of ±115
ppm minimum (MK3727D)
VCXO input tuning voltage 0 to 3.3 V
Packaged in 8 pin SOIC (150 mil wide)
MK3727D is Recommended for New Designs.
VIN
12-18 MHz
P u lla b le
C ry s ta l
X1
X2
Voltage
Controlled
Crystal
O sc illato r
PLL
Frequency
Doubler
24-36 MHz
(2x Crystal Frequency)
MDS 3727 E
1
Revision 052901
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com

1 page




MK3727S pdf
MK3727
LOW COST 24 - 36 MHZ 3.3 VOLT VCXO
DC Electrical Characteristics
VDD=3.3V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol Conditions
Min. Typ.
Operating Voltage
VDD
3.15
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
VOH
VOL
VOH
IOH = -12 mA
IOL = 12 mA
IOH = -4 mA
2.4
VDD-0.4
Operating Supply Current
IDD Output = 27 MHz,
no load
10
Short Circuit Current
VIN, VCXO Control Voltage
IOS
VIA
±50
0
Max.
3.45
0.4
Units
V
V
V
V
mA
mA
3.3 V
AC Electrical Characteristics
VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Output Frequency
MK3727D and
MK3727C
FO VCXO Crystal frequency =
1/2 Output
24
36 MHz
MK3727A and
MK3727S
FO VCXO Crystal frequency =
13.5 MHz
27 MHz
Crystal Pullability
MK3727D and
MK3727C
FP 0V< VIN < 3.3V, Note 1
+ 115
ppm
MK3727A and
MK3727S
FP 0V< VIN < 3.3V, Note 1
+ 100
ppm
VCXO Gain
MK3727D
VIN = VDD/2 + 1V, Note 1
120 ppm/V
MK3727C
VIN = VDD/2 + 1V, Note 1
150 ppm/V
MK3727A
VIN = VDD/2 + 1V, Note 1
170 ppm/V
MK3727S
VIN = VDD/2 + 1V, Note 1
100 ppm/V
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Maximum Output Jitter,
short term
tOR 0.8 to 2.0V, CL=15pF
1.5 ns
tOF 2.0 to 0.8V, CL=15pF
1.5 ns
tD Measured at 1.4V, CL=15pF 40 50 60 %
tJ CL=15pF
100 ps
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
MDS 3727 E
5
Revision 052901
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com

5 Page










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