PDF MCM69P735 Data sheet ( Hoja de datos )

Número de pieza	MCM69P735
Descripción	128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69P735/D Product Preview MCM69P735 128K x 36 Bit Pipelined BurstRAM™ Synchronous Fast Static RAM The MCM69P735 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. It is organized as 128K words of 36 bits each. This device integrates input registers, an output register, a 2–bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and linear burst order (LBO) are clock (K) controlled through positive– edge–triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM69P735 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchro- nous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, pipelined SRAMs output data is temporarily stored by an edge–triggered output register and then released to the output buffers at the next rising edge of clock (K). The MCM69P735 operates from a 3.3 V core power supply and all outputs operate on a 3.3 V or 2.5 V power supply. All inputs and outputs are JEDEC stan- dard JESD8–5 compatible. ZP PACKAGE PBGA CASE 999–01 • MCM69P735 Speed Options Speed 200 MHz tKHKH 5 ns Pipelined tKHQV 2.5 ns Setup 0.5 ns Hold 1 ns IDD 475 mA Pkg PBGA 180 MHz 5.5 ns 3.0 ns 0.5 ns 1 ns 450 mA PBGA 166 MHz 6 ns 3.5 ns 0.5 ns 1 ns 425 mA PBGA • 3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O Supply • ADSP, ADSC, and ADV Burst Control Pins • Selectable Burst Sequencing Order (Linear/Interleaved) • Single–Cycle Deselect Timing • Internally Self–Timed Write Cycle • Byte Write and Global Write Control • PB1 Version 2.0 Compatible • JEDEC Standard 119–Pin PBGA Package BurstRAM is a trademark of Motorola, Inc. The PowerPC name is a trademark of IBM Corp., used under license therefrom. This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. 6/10/97 ©MMOoTtoOrolRa,OIncL.A19F97AST SRAM MCM69P735 1 1 page TRUTH TABLE (See Notes 1 Through 5) Next Cycle Address Used SE1 SE2 SE3 ADSP ADSC ADV G 3 DQx Write 2, 4 Deselect None 1 X X X 0 X X High–Z X Deselect None 0X1 0 X X X High–Z X Deselect None 00X 0 X X X High–Z X Deselect None XX1 1 0 X X High–Z X Deselect Begin Read Begin Read None X0X 1 External 0 1 0 0 External 0 1 0 1 0 X X High–Z X X X X High–Z X5 0 X X High–Z READ5 Continue Read Next XXX 1 1 0 1 High–Z READ Continue Read Next XXX 1 1 0 0 DQ READ Continue Read Next 1XX X 1 0 1 High–Z READ Continue Read Next 1XX X 1 0 0 DQ READ Suspend Read Current X X X 1 1 1 1 High–Z READ Suspend Read Current X X X 1 1 1 0 DQ READ Suspend Read Current 1 X X X 1 1 1 High–Z READ Suspend Read Current 1 X X X 1 1 0 DQ READ Begin Write External 0 1 0 1 0 X X High–Z WRITE Continue Write Next XXX 1 1 0 X High–Z WRITE Continue Write Next 1XX X 1 0 X High–Z WRITE Suspend Write Current X X X 1 1 1 X High–Z WRITE Suspend Write Current 1 X X X 1 1 X High–Z WRITE NOTES: 1. X = don’t care. 1 = logic high. 0 = logic low. 2. Write is defined as either (a) any SBx and SW low or (b) SGW is low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times. 5. This read assumes the RAM was previously deselected. LINEAR BURST ADDRESS TABLE (LBO = VSS) 1st Address (External) 2nd Address (Internal) X . . . X00 X . . . X01 X . . . X01 X . . . X10 X . . . X10 X . . . X11 X . . . X11 X . . . X00 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10 INTERLEAVED BURST ADDRESS TABLE (LBO = VDD) 1st Address (External) 2nd Address (Internal) X . . . X00 X . . . X01 X . . . X01 X . . . X00 X . . . X10 X . . . X11 X . . . X11 X . . . X10 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00 WRITE TRUTH TABLE Cycle Type Read Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write All Bytes SGW H H H H H H H L SW H L L L L L L X SBa SBb SBc SBd XXXX HHHH L HHH H L HH LHLH HLHL LLLL XXXX MOTOROLA FAST SRAM MCM69P735 5 5 Page MOTOROLA FAST SRAM MCM69P735 11 11 Page

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