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PDF MCM6709BRJ6 Data sheet ( Hoja de datos )
| Número de pieza | MCM6709BRJ6 | |
| Descripción | 64K x 4 Bit Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
64K x 4 Bit Static RAM
The MCM6709BR is a 262,144 bit static random access memory organized as
65,536 words of 4 bits. Static design eliminates the need for external clocks or
timing strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6709BR meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 28 lead plastic surface–mount SOJ package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs are TTL Compatible
• Center Power and I/O Pins for Reduced Noise
• Three State Outputs
• Fast Access Times:
MCM6709BR–6 = 6 ns
MCM6709BR–7 = 7 ns
MCM6709BR–8 = 8 ns
BLOCK DIAGRAM
A
A
A
A
A
A
ROW
••
DECODER •
MEMORY MATRIX
512 ROWS x 128 x 4
COLUMNS
A
A
A
DQ
COLUMN I/O
••
••
•
••
•
INPUT
DATA
COLUMN DECODER
•
CONTROL
DQ
AA A AAA A
E
W
G
Order this document
by MCM6709BR/D
MCM6709BR
J PACKAGE
300 MIL SOJ
CASE 810B–03
PIN ASSIGNMENT
A1
A2
A3
A4
E5
DQ 6
VCC 7
VSS 8
DQ 9
W 10
A 11
A 12
A 13
A 14
28 A
27 A
26 A
25 A
24 G
23 DQ
22 VSS
21 VCC
20 DQ
19 A
18 A
17 A
16 A
15 NC
PIN NAMES
A . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ . . . . . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must
be connected for proper operation of the
device.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
3/17/97
M© OMoTtoOroRla,OInLc.A19F97AST SRAM
MCM6709BR
1
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6709BR–6 MCM6709BR–7 MCM6709BR–8
Parameter
Symbol
Min
Max
Min
Max
Min
Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
tAVAV
6
—
7
—
8
— ns 3
tAVWL
0
—
0
—
0
— ns
tAVWH
6
—
7
—
8
— ns
tWLWH
6
—
7
—
8
— ns
tWLEH
Data Valid to End of Write
tDVWH
3
— 3.5 — 3.5 — ns
Data Hold Time
tWHDX
0
—
0
—
0
— ns
Write Low to Data High–Z
tWLQZ
—
3.5
—
3.5
—
3.5 ns 4, 5, 6
Write High to Output Active
tWHQX
3
—
3
—
3
— ns 4, 5, 6
Write Recovery Time
tWHAX
0
—
0
—
0
— ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady state voltage with load of Figure 1b.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
tAVAV
tAVWL
HIGH–Z
tAVWH
tWLQZ
tWLWH
tWLEH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6709BR
5
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| PDF Descargar | [ Datasheet MCM6709BRJ6.PDF ] | |
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