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PDF MCM6706R Data sheet ( Hoja de datos )
| Número de pieza | MCM6706R | |
| Descripción | 32K x 8 Bit Static Random Access Memory | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6706R/D
32K x 8 Bit Static Random Access
Memory
The MCM6706R is a 262,144 bit static random access memory organized as
32,768 words of 8 bits, fabricated using high performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706R meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.
• Single 5.0 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: MCM6706R–6 = 6 ns
MCM6706R–7 = 7 ns
MCM6706R–8 = 8 ns
• Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
A
A VCC
VSS
A
A MEMORY
A
ROW
MATRIX
DECODER
512 ROWS x 64 x 8
A COLUMNS
A
A
A
DQ0 COLUMN I/O
INPUT
DATA
COLUMN DECODER
CONTROL
DQ7
A AA A AA
E
W
G
MCM6706R
J PACKAGE
300 MIL SOJ
CASE 857–02
PIN ASSIGNMENT
A0 1
A1 2
A2 3
A3 4
E5
DQ0 6
DQ1 7
VCC 8
VSS 9
DQ2 10
DQ3 11
W 12
A4 13
A5 14
A6 15
A7 16
32 NC
31 A14
30 A13
29 A12
28 G
27 DQ7
26 DQ6
25 VSS
24 VCC
23 DQ5
22 DQ4
21 A11
20 A10
19 A9
18 A8
17 NC
PIN NAMES
A0 – A14 . . . . . . . . . . . . . . . . . . Address
W . . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ7 . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . No Connection
REV 1
5/95
M© OMoTtoOroRla,OInLc.A19F95AST SRAM
MCM6706R
1
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6706R–6 MCM6706R–7 MCM6706R–8
Parameter
Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time
tAVAV
6
—
7
—
8
— ns 3
Address Setup Time
Address Valid to End of Write
tAVWL
0
—
0
—
0
— ns
tAVWH
6
—
7
—
8
— ns
Write Pulse Width
tWLWH,
6
—
7
—
8
— ns
tWLEH
Data Valid to End of Write
tDVWH
3
— 3.5 —
4
— ns
Data Hold Time
Write Low to Data High–Z
tWHDX
tWLQZ
0
0
—0—0
3.5 0 3.5 0
— ns
4 ns 4, 5, 6
Write High to Output Active
tWHQX
3
—
3
—
3
— ns 4, 5, 6
Write Recovery Time
tWHAX
0
—
0
—
0
— ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
5. Parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is < tWHQX min both for a given device and from device to device.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
tAVAV
tAVWL
HIGH–Z
tWLQZ
tAVWH
tWLEH
tWLWH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6706R
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MCM6706R.PDF ] | |
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