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PDF MCM44256B Data sheet ( Hoja de datos )

Número de pieza MCM44256B
Descripción 4MB R4000 Secondary Cache Fast Static RAM Module Set
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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No Preview Available ! MCM44256B Hoja de datos, Descripción, Manual

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4MB R4000 Secondary Cache Fast
Static RAM Module Set
Four MCM44256B modules comprise a full 4 MB of secondary cache for the
R4000 processor. Each module contains nine MCM6729DWJ fast static RAMs
for a cache data size of 256K x 36. The tag portion, dependent on word line size,
contains either two MCM6729DWJ or one MCM6726DWJ fast static RAMs. All
input signals, except A0 and WE are buffered using 74FBT2827 drivers with se-
ries 25 resistors.
The MCM6729DWJ and MCM6726DWJ are fabricated using high–perfor-
mance silicon–gate BiCMOS technology. Static design eliminates the need for
internal clocks or timing strobes.
All 4MB R4000 supported secondary cache options are available.
Single 5 V ± 10% Power Supply
All Inputs and Outputs are TTL Compatible
Fast Module Access Time: 12/15/17 ns
Zero Wait–State Operation
Unified or Split Secondary Cache is Supported
Word Line Sizes of 4, 8, 16, and 32 are Available (See Ordering
Information for Details)
Decoupling Capacitors are Used for Each Fast Static RAM and Buffer,
Along with Bulk Capacitance for Maximum Noise Immunity
High Quality Multi–Layer FR4 PWB with Separate Power and Ground
Planes
PIN NAMES
A0 – A17 . . . . . . . . . . . . . . . . Address Inputs
WE . . . . . . . . . . . . . . . . . . . . . . . Write Enable
DCS . . . . . . . . . . . . . . . . . . . . . . Data Enable
TCS . . . . . . . . . . . . . . . . . . . . . . . Tag Enable
OE . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ35 . . . . . . . . . Data Input / Output
TDQ0 – TDQ7 . . . TAG Data Input / Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
For proper operation of the device, VSS must
be connected to ground.
11/19/97
©MMOoTtoOrolRa,OIncL.A19F97AST SRAM
Order this document
by MCM44256B/D
MCM44256B
Series
PIN ASSIGNMENT
80 LEAD SIMM — TOP VIEW
VCC
DQ1
DQ3
DQ5
VSS
DQ8
DQ10
DQ12
DQ14
DQ15
DQ17
DQ19
DQ21
VSS
DQ23
DQ25
DQ27
DQ29
DQ30
DQ32
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1 VSS
3 DQ0
5 DQ2
7 DQ4
9 DQ6
11 DQ7
13 DQ9
15 DQ11
17 DQ13
19 VSS
21 DQ16
23 DQ18
25 DQ20
27 DQ22
29 VCC
31 DQ24
33 DQ26
35 DQ28
37 VSS
39 DQ31
DQ34
VSS
A0
A2
A4
A6
42
44
46
48
50
52
VCC 54
OE 56
A8 58
A10 60
VSS 62
A13 64
A15 66
A17 68
TDQ0 70
TDQ1 72
TDQ3 74
TDQ5
TDQ7
VSS
76
78
80
41 DQ33
43 DQ35
45 WE
47 A1
49 A3
51 A5
53 VSS
55 DCS
57 A7
59 A9
61 A11
63 A12
65 A14
67 A16
69 TCS
71 VSS
73 TDQ2
75 TDQ4
77 TDQ6
79 VCC
MCM44256B SERIES
1

1 page




MCM44256B pdf
A1 – A17
READ CYCLE 1 (See Note)
tAVQV
A0
Q (DATA OUT)
tA0XQX
tAXQX
PREVIOUS DATA VALID
tA0VQV
NOTE: Module is continuously selected (DCS or TCS = VIL, OE = VIL).
A1 – A17
READ CYCLE 2 (See Note)
tAVQV
A0
DCS/TCS
(DATA/TAG ENABLE)
OE (OUTPUT ENABLE)
Q (DATA OUT)
tA0VQV
tELQV
tELQX
tGLQX
tGLQV
NOTE: Address valid prior to or coincident with DCS or TCS going low.
DATA VALID
tEHQZ
tGHQZ
DATA VALID
MOTOROLA FAST SRAM
MCM44256B SERIES
5

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