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PDF MCF5249PB Data sheet ( Hoja de datos )
| Número de pieza | MCF5249PB | |
| Descripción | system controller/decoder | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Product Brief
MCF5249PB/D
Rev. 0, 3/2002
MCF5249 Integrated
ColdFire® Microprocessor
Product Brief
Freescale Semiconductor, Inc.
This document provides an overview of the MCF5249 ColdFire® processor and general
descriptions of MCF5249 features and modules.
The MCF5249 was designed as a system controller/decoder for MP3 music players, especially
portable MP3 CD players. The 32-bit ColdFire core with Enhanced Multiply Accumulate
(EMAC) unit provides optimum performance and code density for the combination of control
code and signal processing required for MP3 decode, file management, and system control.
Low power features include a hardwired CD ROM decoder, advanced 0.18um CMOS process
technology, 1.8V core power supply, and on-chip 96 Kbyte SRAM. MP3 decode requires less
than 20 MHz CPU bandwidth and runs in on-chip SRAM with external access only for data
input and output.
The MCF5249 is also an excellent general purpose system controller with over 125
Dhrystone 2.1 MIPS @ 140 MHz performance at a very competitive price. The integrated
peripherals and EMAC allow the MCF5249 to replace both the microcontroller and the DSP
in certain applications. Most peripheral pins can also be remapped as general-purpose I/O
pins.
1.1 MCF5249 Features: Introduction
The MCF5249 integrated microprocessor combines a Version 2 ColdFire® processor core
operating at 140 MHz with the following modules:
• DMA controller with 4 DMA channels
• Integrated Enhanced Multiply-accumulate Unit (EMAC)
• 8-Kbyte Direct Mapped Instruction Cache
• 96-Kbyte SRAM (a 64K and 32K bank)
• Operates from external crystal oscillator
• Supports 16-bit wide SDRAM memories
• Serial Audio Interface which supports IIS and EIAJ audio protocols
• Digital audio transmitter and two receivers compliant with IEC958 audio protocol
• CD-ROM and CD-ROM XA block decoding and encoding function
• Two UARTs
• Queued Serial Peripheral Interface (QSPI) (Master Only)
• Two timers
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
MCF5249 Features: Details
• Audio Interfaces
— IEC958 input and output
— Four serial Philips IIS/Sony EIAJ interfaces
– One with input and output, one with output only, two with input only (Three inputs, two
outputs)
– Master and Slave operation
• CD Text Interface
— Allows the interface of CD subcode (transmitter only)
• Dual Universal Synchronous/Asynchronous Receiver/Transmitter (Dual UART)
— Full duplex operation
— Baud-rate generator
— Modem control signals: clear-to-send (CTS) and request-to-send (RTS)
— DMA interrupt capability
— Processor-interrupt capability
• Queued Serial Peripheral Interface (QSPI)
— Programmable queue to support up to 16 transfers without user intervention
— Supports transfer sizes of 8 to 16 bits in 1-bit increments
— Four peripheral chip-select lines for control of up to 15 devices
— Baud rates from 273 Kbps to 17.5 Mbps at 140MHz
— Programmable delays before and after transfers
— Programmable clock phase and polarity
— Supports wraparound mode for continuous transfers
— Master mode only
• Dual 16-bit General-purpose Multimode Timers
— Clock source selectable from external, CPU clock/2 and CPU clock/32.
— 8-bit programmable prescaler
— 2 timer inputs and 2 outputs
— Processor-interrupt capability
— 14.3 nS resolution with CPU clock at 140MHz
• IDE/ SmartMedia Interface
— Allows direct connection to an IDE hard drive or other IDE peripheral
• Analog/Digital Converter
— 12-Bit Resolution
— 4 Muxed inputs
• Flash Memory Card Interface
— Allows connection to Sony MemoryStick compatible devices
— Support SD cards and other types of flash media
MOTOROLA
MCF5249 Integrated ColdFire® Microprocessor Product Brief
For More Information On This Product,
Go to: www.freescale.com
5
5 Page 
Freescale Semiconductor, Inc.
MCF5249 Functional Overview
1.5.17 Analog/Digital Converter (ADC)
The four channel ADC is based on the Sigma-Delta concept with 12-bit resolution. The digital portion of
the ADC is provided internally. The analog voltage comparator must be provided externally as well as an
external integrator circuit (resistor/capacitor) which is driven by the ADC output. A software interrupt is
provided when the ADC measurement cycle is complete.
1.5.18 Flash Memory Card Interface
The interface is Sony MemoryStick and SecureDigital compatible. However, there is no hardware support
for MagicGate™.
1.5.19 I2C Module
The two-wire I2C bus interface, which is compliant with the Philips I2C bus standard, is a bidirectional serial
bus that exchanges data between devices. The I2C bus minimizes the interconnection between devices in the
end system and is best suited for applications that need occasional bursts of rapid communication over short
distances among several devices. Bus capacitance and the number of unique addresses limit the maximum
communication length and the number of devices that can be connected.
1.5.20 Chip-Selects
There are four programmable chip selects on the MCF5249:
• Two programmable chip-select outputs (CS0 and CS1) provide signals that enable glueless
connection to external memory and peripheral circuits. The base address, access permissions, and
automatic wait-state insertion are programmable with configuration registers. These signals also
interface to 16-bit ports.
• Two dedicated chip selects (CS2 and CS3) are used for the IDE and/or SmartMedia interface
CS0 is active after reset to provide boot-up from external FLASH/ROM.
1.5.21 GPIO Interface
A total of 44 General Purpose inputs and 46 General Purpose outputs are available. These are multiplexed
with various other signals. Eight of the GPIO inputs have edge sensitive interrupt capability.
1.5.22 Interrupt Controller
The interrupt controller provides user-programmable control of a total of 57 interrupts. There are 49 internal
interrupt sources. In addition, there are 8 GPIOs where interrupts can be generated on the rising or falling
edge of the pin. All interrupts are autovectored and interrupt levels are programmable.
1.5.23 JTAG
To help with system diagnostics and manufacturing testing, the MCF5249 includes dedicated
user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability, often
referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1A standard.
Motorola provides BSDL files for JTAG testing.
MOTOROLA
MCF5249 Integrated ColdFire® Microprocessor Product Brief
For More Information On This Product,
Go to: www.freescale.com
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MCF5249PB.PDF ] | |
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