|
|
PDF MC92501 Data sheet ( Hoja de datos )
| Número de pieza | MC92501 | |
| Descripción | ATM Cell Processor | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MC92501 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
ATM Cell Processor
The ATM Cell Processor (MC92501) is an Asynchronous Transfer Mode (ATM)
layer device composed of dedicated high-performance ingress and egress cell
processors combined with UTOPIA Level 2-compliant physical (PHY) and switch
interface ports (see Block Diagram). The MC92501 is a second generation ATM
cell processor in MotorolaÕs 92500 series. This document provides information
on the new features offered by the second generation ATM cell processor. This
document, combined with MC92500/D, provides the complete speciÞcation for
the ATM cell processor.
New Features of the MC92501:
¥ Implements ATM Layer Functions for Broadband ISDN According to ATM
Forum UNI 4.0 and TM 4.0 SpeciÞcations, ITU Recommendations, and
Bellcore Recommendations
¥ Provides ABR Relative Rate Marking and EFCI Marking According to TM 4.0
¥ Selective Discard CLP = 1 (or CLP = 0+1) Flow on Selected Connections
¥ UTOPIA Level 2 PHY Interface and UTOPIA ATM Layer Interface
¥ Supports Both Partial Packet Discard (PPD) and Early Packet Discard (EPD)
¥ Change ABR RM Cell Priority
¥ Support for CLP Transparency
Existing MC92500 Features:
¥ Full-Duplex Operation at Data Rates up to 155 Mbit/sec
¥ Performs Internal VPI and VCI Address Compression for up to 64K VCs
¥ CLP-Aware Peak, Average, and Burst-Length Policing with Programmable
Tag/Drop Action Per Policer
¥ Supports up to 16 Physical Links Using Dedicated Ingress/Egress MultiPHY
Control Signals
¥ Each Physical Link Can Be ConÞgured as Either a UNI or NNI Port
¥ Supports Multicast, Multiport Address Translation
¥ Maintains Both Virtual Connection and Physical Link Counters on Both
Ingress and Egress Cell Flows
¥ Provides a Flexible 32-Bit External Memory Port for Context Management
¥ Automated AIS, RDI, CC, and Loopback Functions with Performance
Monitoring Block Test on All 64K Connections
¥ Programmable 32-Bit Microprocessor Interface Supporting Big-Endian or
Little-Endian Bus Formats
¥ Bidirectional UPC or NPC Design with up to Four Leaky Buckets Per
Connection
¥ Supports a Programmable Number of Additional Switch Overhead
Parameters Allowing Adaptation to Any Switch Routing Header Format
¥ Provides Per-Link Cell Counters in Both Directions
Order this document
by MC92501/D
MC92501
GC SUFFIX
GTBGA
CASE 1208
ORDERING INFORMATION
MC92501GC GTBGA
This document contains information on a new product. SpeciÞcations and information herein are subject to change without notice.
REV 1.2
2/98
TN98020500
M© MOoTtoOrolRa,OInLc.A1998
MC92501
1
1 page  
SECTION 1. ATM NETWORK
1.1. ATM Network Description
A typical ATM network consists of user end stations that
transmit and receive 53-byte data cells on virtual connections
(see Figure 1). Physical links and switching systems
interconnect the virtual connections. A virtual connectionÕs
path is established at the beginning of the data transfer,
maintained while the end-stations are communicating, and
torn down after the transfer is complete. This transmission
method increases the transfer speed because the
determination of the path the data will take is done only at the
beginning of the data transfer instead of when each data sub-
block or packet is transferred.
On a given physical link, each connection is assigned a
unique connection identiÞer. The connection identiÞer is
placed in the header of each cell by the transmitting equipment
and is used by the receiving equipment to route the cell to the
next physical link on the connection path. All cells belonging
to a speciÞc virtual connection follow the identical path from
the transmitting end station through the switching systems to
the receiving end station.
An ATM switch contains a high-speed switching fabric that
connects multiple line cards.The switching fabric connects the
input port to the output port based on the switchÕs routing table.
The line card interfaces between the physical medium and the
switching fabric by recovering incoming cells from the arriving
bit stream or converting outgoing cells into a bit stream for
transmission. An ATM swtich partitioned in this fashion can
efÞciently handle multiple physical links by independently
transferring each incoming ATM cell from its source port to its
destination port, based on the switchÕs routing table.
ATM standards divide the tasks to be performed on each
side of the switch fabric into PHY layer and ATM layer tasks.
The PHY layer tasks are dependent on the physical medium
that connects ATM switches. The ATM layer tasks operate at
the cell level and are independent of the physical medium.
VCs
END STATIONS
Switch
Switch
Switch
Switch
Switch
VCs
Switch
END STATIONS
SWITCH
LINE
CARD
SWITCHING FABRIC
LINE
CARD
CLK REC
PHY
MC92501
ATM LAYER FUNCTIONS
LINE CARD
Figure 1. MC92501 in an ATM Network Application
MOTOROLA
MC92501
5
5 Page 
SECTION 4. SELECTIVE DISCARD
ATM Forum TM 4.0 deÞnes procedures according to which
cells can be discarded by network elements. A switching
element may discard cells belonging to selected connections
or cells whose CLP = 1 in case of congestion. This function is
called selective discard and it is implemented by the
MC92501. Selective discard is enabled by the ICNGÑGlobal
Ingress Congestion NotiÞcation bit in the Ingress Processing
Control Register (IPLR). Selective discard can be enabled on
a per-connection basis by the ISDMÑIngress Selective
Discard Operation Mode Þeld in the Common Parameters
Extension Word. This Þeld determines whether selective
discard is enabled and whether selective discard is performed
on CLP = 1 or on CLP = 0+1 trafÞc. Selective discard can be
enabled globally by the IPCVÑIngress Enable bit in the ATMC
CFB ConÞguration Register (ACR).
MOTOROLA
MC92501
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MC92501.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MC92500 | ATM Cell Processor | Motorola Semiconductors |
| MC92500ZQ | ATM Cell Processor | Motorola Semiconductors |
| MC92501 | ATM Cell Processor | Motorola Semiconductors |
| MC92501GC | ATM Cell Processor | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |