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PDF MAX5201BEUB Data sheet ( Hoja de datos )
| Número de pieza | MAX5201BEUB | |
| Descripción | Low-Cost / Voltage-Output / 16-Bit DACs with Internal Reference in MAX | |
| Fabricantes | Maxim Integrated | |
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19-2655; Rev 1; 1/03
Low-Cost, Voltage-Output, 16-Bit DACs with
Internal Reference in µMAX
General Description
The MAX5200–MAX5203 serial input, voltage-output,
16-bit digital-to-analog converters (DACs) provide
monotonic 16-bit output over temperature without any
adjustments. The MAX5200/MAX5201 operate from a
+5V single power supply featuring an internal reference
of +2.5V and an internal gain of 2, while the MAX5202/
MAX5203 operate from a +3V or +3.3V single power
supply featuring an internal reference of +1.5V and an
internal gain of 2. The MAX5200–MAX5203 DAC output
range is typically from 0 to VDD.
The MAX5200–MAX5203 feature a hardware reset input
(CLR) that, when pulled low, clears the output to zero
code 0000 hex (MAX5201/MAX5203) or resets the out-
put to midscale code 8000 hex (MAX5200/MAX5202).
The 3-wire serial interface is compatible with
SPI™/QSPI™/MICROWIRE™. All devices have a low-
power shutdown mode that reduces the supply current
consumption to 1µA.
The MAX5200–MAX5203 are available in a space-sav-
ing 10-pin µMAX package and are guaranteed over the
extended temperature range (-40°C to +105°C). Refer
to the MAX5204–MAX5207 data sheet for external refer-
ence versions.
Features
o Guaranteed 16-Bit Monotonic
o Internal Reference
o 10-Pin 5mm ✕ 3mm µMAX Package
o Rail-to-Rail® Output Amplifier
o Single-Supply Operation
+5V (MAX5200/MAX5201)
+3V, +3.3V (MAX5202/MAX5203)
o Low Power Consumption: 0.8mA
o Shutdown Mode Reduces Supply Current to 1µA
o SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial
Interface
o Power-On-Reset Sets Output to
Midscale (MAX5200/MAX5202)
Zero Scale (MAX5201/MAX5203)
Applications
Low-Cost VCO/VCXO Frequency Control
Industrial Process Control
High-Resolution Offset Adjustment
Pin Configuration
TOP VIEW
CLR 1
REF 2
AGND 3
VDD 4
OUT 5
MAX5200–
MAX5203
10 DGND
9 SCLK
8 DIN
7 LDAC
6 CS
µMAX
PART
MAX5200AEUB
MAX5200BEUB
MAX5200ACUB
MAX5201AEUB
MAX5201BEUB
MAX5201ACUB
MAX5202AEUB
MAX5202BEUB
MAX5202ACUB
MAX5203AEUB
MAX5203BEUB
MAX5203ACUB
Ordering Information
TEMP RANGE
-40°C to +105°C
-40°C to +105°C
0°C to +105°C
-40°C to +105°C
-40°C to +105°C
0°C to +105°C
-40°C to +105°C
-40°C to +105°C
0°C to +105°C
-40°C to +105°C
-40°C to +105°C
0°C to +105°C
PIN-PACKAGE
10 µMAX
10 µMAX
10 µMAX
10 µMAX
10 µMAX
10 µMAX
10 µMAX
10 µMAX
10 µMAX
10 µMAX
10 µMAX
10 µMAX
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
Selector Guide appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Low-Cost, Voltage-Output, 16-Bit DACs with
Internal Reference in µMAX
ELECTRICAL CHARACTERISTICS—MAX5202/MAX5203 (continued)
(VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), output load = 10kΩ in parallel with 250pF, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
INTERNAL REFERENCE
VREF Output Voltage
TA = +25°C
VREF Tempco
TA = 0°C to +70°C
TA = -40°C to +85°C
DIGITAL INPUTS (DIN, SCLK, CS, CLR, LDAC)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
VHYST
Input Leakage
IIN Digital inputs = 0 or VDD
Input Capacitance
CIN
POWER REQUIREMENTS
Positive Power Supply
VDD
Positive Supply Current
IDD All digital inputs at 0 or VDD (Note 5)
Shutdown Supply Current
ISHDN All digital inputs at 0 or VDD
TIMING CHARACTERISTICS
SCLK Frequency
fSCLK
SCLK Clock Period
tCP
SCLK Pulse Width High
tCH
SCLK Pulse Width Low
tCL
DIN Setup Time
tDS
DIN Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SCLK Rise to CS Fall Ignore
CS Rise to SCLK Rise Ignore
LDAC Pulse Width
CS Rise to LDAC Low Setup
SCLK Fall to CS Fall Ignore
CS Pulse Width Low for Shutdown
CS Pulse Width High
tDH
tCSS
tCSH
tCS0
tCS1
tLDAC
tLDACS
tCSOL
tCSWL
tCSWH
1.46 1.5 1.54
V
±15
ppm/°C
±20
2.1
0.6
200
±1
15
V
V
mV
µA
pF
2.7 3.6 V
0.8 1.5 mA
1 10 µA
10 MHz
100 ns
40 ns
40 ns
40 ns
0 ns
40 ns
0 ns
10 ns
40 ns
40 ns
40 ns
10 ns
40 ns
100 ns
Note 1: Static performance tested at VDD = +5.0V (MAX5200/MAX5201) and at VDD = +3.0V (MAX5202/MAX5203).
Note 2: INL and DNL are guaranteed for outputs between 0.5V to (VDD - 0.5V).
Note 3: Guaranteed monotonic.
Note 4: VREF = 2.5V (MAX5200/MAX5201) and VREF = 1.5V (MAX5202/MAX5203).
Note 5: RL = ∞, digital inputs are at VDD or DGND.
_______________________________________________________________________________________ 5
5 Page 
Low-Cost, Voltage-Output, 16-Bit DACs with
Internal Reference in µMAX
VDD
10µF
MC68XXXX
PCS0
MOSI
SCLK
0.1µF
CLR
CS
DIN
SCLK
MAX5200–
MAX5203
LDAC DGND AGND REF
OUT
+5V
MAX400
-5V
BIPOLAR
OUT
(±VREF)
Figure 5. MAX5200–MAX5203 Typical Operating Circuit—Bipolar Output
Table 1. Bipolar Code Table
DAC LATCH CONTENTS
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
ANALOG OUTPUT, VOUT
+VREF × (32,767 / 32,768)
+VREF × (1 / 32,768)
0V
-VREF × (1 / 32,768)
-VREF × (32,768 / 32,768)
Bipolar Configuration
The MAX5200–MAX5203 are designed for unipolar opera-
tion, but can be used in bipolar applications with an exter-
nal amplifier and resistors. Figure 5 shows the
MAX5200–MAX5203 configured for bipolar operation. The
op amp is set for unity gain. Table 1 lists the offset binary
code for this circuit. The output voltage range is ±VREF.
Layout Considerations
Digital and AC transient signals coupling to AGND can
create noise at the output. Connect AGND to the high-
est quality ground available. Use proper grounding
techniques, such as a multilayer board with a low-
inductance ground plane. Wire-wrapped boards and
sockets are not recommended. For optimum system
performance, use printed circuit (PC) boards with sep-
arate analog and digital ground planes. Connect the
two ground planes together at the low-impedance
power-supply source. Connect DGND and AGND pins
together at the IC. The best ground connection is
achieved by connecting the DAC’s DGND and AGND
together, and then connecting that point to the system
analog ground plane. If the DAC’s DGND is connected
to the system digital ground, digital noise can get
through the DAC’s analog portion.
Chip Information
TRANSISTOR COUNT: 8764
PROCESS: BiCMOS
______________________________________________________________________________________ 11
11 Page | ||
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