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PDF MAX5123AEEE Data sheet ( Hoja de datos )
| Número de pieza | MAX5123AEEE | |
| Descripción | +5V/+3V / 12-Bit / Serial / Force/Sense DACs with 10ppm/C Internal Reference | |
| Fabricantes | Maxim Integrated | |
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19-1446; Rev 0; 3/99
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
General Description
The MAX5122/MAX5123 low-power, 12-bit, voltage-out-
put, digital-to-analog converters (DACs) feature an inter-
nal precision bandgap reference and output amplifier.
The MAX5122 operates on a single +5V supply with an
internal +2.5V reference, and offers a configurable output
amplifier. If necessary, the user can override the on-chip,
<10ppm/°C voltage reference with an external reference.
The MAX5123 has the same features as the MAX5122 but
operates from a single +3V supply and has an internal
+1.25V precision reference. The user-accessible inverting
input and output of the amplifier allows specific gain con-
figurations, remote sensing, and high output drive capa-
bility for a wide range of force/sense applications. Both
devices draw only 500µA of supply current, which
reduces to 3µA in power-down mode. In addition, their
power-up reset feature allows for a user-selectable initial
output state of either 0V or midscale and reduces output
glitches during power-up.
The serial interface is compatible with SPI™, QSPI™, and
MICROWIRE™, which makes the MAX5122/MAX5123
suitable for cascading multiple devices. Each DAC has
a double-buffered input organized as an input register
followed by a DAC register. A 16-bit shift register loads
data into the input register. The DAC register may be
updated independently or simultaneously with the input
register.
Both devices are available in a 16-pin QSOP package
and are specified for the extended-industrial (-40°C to
+85°C) operating temperature range. For pin-compatible
14-bit upgrades, see the MAX5171/MAX5173 data sheet;
for the pin-compatible 13-bit version, see the MAX5132/
MAX5133 data sheet.
Applications
Industrial Process Control
Automatic Test Equipment
Digital Offset and Gain Adjustment
Motion Control
Microprocessor-Controlled Systems
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Features
o Single-Supply Operation
+5V (MAX5122)
+3V (MAX5123)
o Built-In 10ppm/°C max Precision Bandgap Reference
+2.5V (MAX5122)
+1.25V (MAX5123)
o SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial
Interface
o Pin-Programmable Shutdown Mode and Power-
Up Reset (0 or Midscale Output Voltage)
o Buffered Output Capable of Driving 5kΩ 100pF
or 4–20mA Loads
o Space-Saving 16-Pin QSOP Package
o Pin-Compatible 13-Bit Upgrades Available
(MAX5132/MAX5133)
o Pin-Compatible 14-Bit Upgrades Available
(MAX5171/MAX5173)
PART
MAX5122AEEE
MAX5122BEEE
MAX5123AEEE
MAX5123BEEE
Ordering Information
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
16 QSOP
16 QSOP
16 QSOP
16 QSOP
INL
(LSB)
±0.5
±1
±1
±2
Pin Configuration
TOP VIEW
FB 1
OUT 2
RSTVAL 3
PDL 4
CLR 5
CS 6
DIN 7
SCLK 8
MAX5122
MAX5123
QSOP
16 VDD
15 REFADJ
14 REF
13 AGND
12 PD
11 UPO
10 DOUT
9 DGND
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
TIMING CHARACTERISTICS—MAX5123 (+3V)
(VDD = +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, output amplifier connected
in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Clock Period
SCLK Pulse Width High
tCP
tCH
150 ns
75 ns
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
tCL
tCSS
tCSH
75 ns
60 ns
0 ns
SDI Setup Time
tDS
60 ns
SDI Hold Time
tDH
0 ns
SCLK Rise to DOUT Valid
Propagation Delay Time
tDO1
CLOAD = 200pF
200 ns
SCLK Fall to DOUT Valid
Propagation Delay Time
SCLK Rise to CS Fall Delay Time
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
tDO2
tCS0
tCS1
tCSW
CLOAD = 200pF
200 ns
10 ns
75 ns
150 ns
Note 1: Accuracy is guaranteed by the following table:
VDD Accuracy Guaranteed
(V) From Code: To Code:
5 16
4095
3 33
4095
Note 2: Offset is measured at the code closest to 10mV.
Note 2: The temperature coefficient is determined by the “box” method, in which the maximum ∆VOUT over the temperature range
is divided by ∆T and the typical reference voltage.
Note 4: Accuracy is better than 1.0LSB for VOUT = 10mV to (VDD - 180mV). Guaranteed by PSR test on end points.
Note 5: RLOAD = ∞and digital inputs are at either VDD or DGND.
_______________________________________________________________________________________ 5
5 Page 
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
The circuit in Figure 3 achieves a nominal reference
adjustment range of ±1%. Connect a 33nF capacitor
from REFADJ to AGND to establish low-noise DAC
operation. Larger capacitor values may be used, but
will result in increased start-up delay. The time constant
(τ) for the start-up delay is determined by the REFADJ
input impedance of 4kΩ and CREFADJ:
τ= 4kΩ · CREFADJ
External Reference
An external reference may be applied to the REF pin.
Disable the internal reference by pulling REFADJ to
VDD. This allows an external reference signal (AC- or
DC-based) to be fed into the REF pin. For proper oper-
ation, do not exceed the input voltage range limits of 0
to (VDD - 1.4V) for VREF.
Determine the output voltage using the following equa-
tion (REFADJ = VDD):
VOUT = VREF [(NB / 4096) G]
where NB is the numeric value of the MAX5122/
MAX5123 input code (0 to 4095), VREF is the external
reference voltage, and G is the gain of the output
amplifier, set by an external resistor-divider. The REF
pin has a minimum input resistance of 40kΩ and is
code-dependent.
Output Amplifier
The MAX5122/MAX5123’s DAC output is internally
buffered by a precision amplifier with a typical slew rate
of 0.6V/µs. Access to the output amplifier’s inverting
input (FB) provides the user greater flexibility with
amplifier gain setting and signal conditioning (see
Applications Information).
The output amplifier typically settles to ±0.5LSB from a
full-scale transition within 20µs when it is connected in
unity gain and loaded with 5kΩ 100pF. Loads less
than 1kΩ may result in degraded performance.
Power-Down Mode
These devices feature software- and hardware-pro-
grammable (PD pin) shutdown modes that reduce the
typical supply current to 3µA. To enter software shut-
down mode, program the control sequence for the DAC
as shown in Table 1.
In shutdown mode, the amplifier output becomes high-
impedance and the serial interface remains active.
Data in the input registers is saved, allowing the
MAX5122/MAX5123 to recall the output state prior to
entering shutdown when returning to normal operation.
To exit shutdown mode, load both input and DAC regis-
ters simultaneously or update the DAC register from the
input register. When returning from shutdown to normal
operation, wait 2ms for the reference to settle. When
using an external reference, the DAC requires only
20µs for the output to stabilize.
+5V
90k MAX5122
400k
100k
REFADJ
33nF
+3V
15k MAX5123
400k
100k
REFADJ
33nF
Figure 3a. MAX5122 Reference Adjust Circuit
Figure 3b. MAX5123 Reference Adjust Circuit
______________________________________________________________________________________ 11
11 Page | ||
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