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PDF MH64S72VJG-5 Data sheet ( Hoja de datos )
| Número de pieza | MH64S72VJG-5 | |
| Descripción | 4 /831 /838 /208-BIT ( 67 /108 /864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72VJG-5,-6
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH64S72VJG is 67108864 - word x 72-bit Sy nchronous
DRAM module. This consist of eighteen industry standard
64M x 4 Sy nchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package prov ides any
application where high densities and large of quantities memory
are required.
This is a socket-ty pe memory m odule ,suitable f or easy
interchange or addition of module.
FEATURES
Max.
Frequency
-5 133MHz
-6 133MHz
Access Time from CLK
[component level]
5.4ns
(CL = 3,4 at Latch mode)
5.4ns
(CL = 4 at Latch mode)
Utilizes industry standard 64M X 4 Synchronous DRAMs in
TSOP package , industrystandard Resistered buffer in TSSOP
package,industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz forFully synchronous operation
referenced to clock rising edge
4-bank operation controlled byBA0,BA1(Bank Address)
/CAS latency-2/3(programmable,at buffer mode)
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst W rite / Single W rite(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
8192 refresh cycles every 64ms
Discrete IC and module design conform to
PC133 specification. -5 for PC133 CL2
-6 for PC133 CL3
APPLICATION
Main memoryor graphic memoryin computer systems
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-0385-0.1
MITSUBISHI
ELECTRIC
27.Feb.2001 1
1 page  
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72VJG-5,-6
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH64S72VJG provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
def ine basic commands
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
term inates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0385-0.1
MITSUBISHI
ELECTRIC
27.Feb.2001 5
5 Page 
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72VJG-5,-6
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
Current State
CKE CKE
n-1 n
/S
/RAS /CAS /WE
Add
Action
SELF -
H X X X X X X INVALID
REFRESH*1 L H H X X X X Exit Self-Refresh(Idle after tRC)
L H L H H H X Exit Self-Refresh(Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Self-Refresh)
POWER
H X X X X X X INVALID
DOWN
L H X X X X X Exit Power Down to Idle
L L X X X X X NOP(Maintain Self-Refresh)
ALL BANKS H H X X X X X Refer to Function Truth Table
IDLE*2
H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
L X X X X X X Refer to Current State = Power Down
ANY STATE H H X X X X X Refer to Function Truth Table
other than H L X X X X X Begin CK0 Suspend at Next Cycle*3
listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3
L L X X X X X Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
MIT-DS-0385-0.1
MITSUBISHI
ELECTRIC
27.Feb.2001 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MH64S72VJG-5.PDF ] | |
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