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PDF MH4V64AXJJ-6S Data sheet ( Hoja de datos )
| Número de pieza | MH4V64AXJJ-6S | |
| Descripción | FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary
Some of contents are subject
to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
DESCRIPTION
ADDRESS
This is family of 4194304 - word by 64 - bit dynamic RAM
Part No.
module. This consists of four industry standard 4Mx16 dynamic
RAMs in TSOP and one industry EEPROM in TSSOP.
MH4V64AXJJ
The mounting of TSOP on a card edge dual in line package MH4V644AXJJ
provides any application where high densities and large of
Row Add. Col Add. Refresh
A0~A12
A0~A11
/RAS only Ref,Normal R/W
A0~A8 CBR Ref,Hidden Ref
A0~A9 /RAS only Ref,Normal R/W
CBR Ref,Hidden Ref
Refresh
Cycle
8192/64ms
4096/64ms
4096/64ms
quantities memory are required.
This is a socket-type memory module,suitable for easy
APPLICATION
interchange of addition of modules.
FEATURES
Main memory unit for computer,Microcomputer
memory,Refresh memory for CRT.
MH4V64AXJJ-5,5S
RAS
access
time
(max.ns)
CAS
access
time
(max.ns)
Address
access
time
(max.ns)
OE
access
time
(max.ns)
Cycle
time
(min.ns)
50 13 25 13 90
*:Applicable to self refresh version(MH4V64/644AXJJ-5S,-6S)
only
MH4V64AXJJ-6,6S
60
15
30
15 110
MH4V644AXJJ-5,5S 50 13 25 13 90
MH4V644AXJJ-6,6S 60 15 30 15 110
single 3.3V± 0.3V supply
Low stand-by power dissipation
7.2mW- - - - - - - - - LVCMOS input level
operating power dissipation
MH4V64AXJJ-5,5S - - - - - 1584 mW(max.)
MH4V64AXJJ-6,6S - - - - - 1440mW(max.)
MH4V644AXJJ-5,5S - - - - 2016 mW(max.)
MH4V644AXJJ-6,6S - - - - 1872 mW(max.)
Self refresh capability*
Self refresh current - - - - 1600 uA(max.)
All input, output LVTTL compatible and low capacitance
Utilizes industry standard 4Mx16 RAMs in TSOP
and industry standard EEPROM in TSSOP.
Includes decoupling capacitor(0.22uFx4)
Fast page mode , Read-modify-write,
CAS before RAS refresh,Hidden refresh capabilities.
Early-write mode,OE to control output buffer
impedance.
MIT-DS-0072-0.5
MITSUBISHI
ELECTRIC
( 1 / 25 )
26/Feb./1997
1 page  
Preliminary
Some of contents are subject
to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V64AXJJ-5S,-6S)
Bytes
Function described
SPD entry data
SPD DATA entry(Hex)
1 Total # bytes of SPD memory device
256 Bytes
08
2 Fundamental memory type
FPM DRAM
01
3 # Row Addresses on this assembly
A0-A12
0D
4 # Column Addresses on this assembly
A0-A8
09
5 # Module Banks on this assembly
1bank
01
6 Data Width of this assembly...
x64
40
7 ... Data Width continuation
0
00
8 Voltage interface standard of this assembly
3.3V LVTTL
02
9
RAS# access time of this assembly
-5S
50ns
32
-6S 60ns
3C
10
CAS# access time of this assembly
-5S
13ns
0D
-6S 15ns
0F
11 DIMM Configuration type (Non-parity,Parity,ECC)
non parity
00
12 Refresh Rate/Type
S/R(15.625uS)
80
13 DRAM width,Primary DRAM
x16
10
14 Error Checking DRAM data width
N/A
00
15-31
Reserved for future offerings
open
00
32-61 Superset Memory type(may be used in future)
open
00
62 SPD Data Revision Code
Rev 1
01
63 Checksum for bytes 0-62
Check sum for -5
B2
Check sum for -6
BE
64-71 Manufacturers JEDEC ID code per JEP-106
MITSUBISHI
1CFFFFFFFFFFFFFF
72 Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
73-90
Manufacturer's Part Number
MH4V64AXJJ-5S 4D483456363441584A4A2D355335532020202020
MH4V64AXJJ-6S 4D483456363441584A4A2D365336532020202020
91-92
Revision Code
PCB revision
rrrr
93-94
Manufacturing date
year/week code
yy/ww
95-98
Assembly Serial Number
serial number
ssssssss
99-125
Manufacturer Specific Data
open
00
126-127
Reserved
open
00
128-255
Open User Free-Form area not defined
open
00
MIT-DS-0072-0.5
MITSUBISHI
ELECTRIC
( 5 / 25 )
26/Feb./1997
5 Page 
Preliminary
Some of contents are subject
to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
SWITCHING CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)
Symbol
Parameter
Limits
-5,-5S
-6,-6S
Unit
tCAC
tRAC
tAA
tCPA
tOEA
tCLZ
tOFF
tOEZ
Min Max Min Max
Access time from /CAS
(Note 7,8)
13
15
Access time from /RAS
(Note 7,9)
50
60
Column address access time
(Note 7,10)
25
30
Access time from /CAS precharge
(Note 7,11)
30
35
Access time from /OE
(Note 7)
13
15
Output low impedance time from /CAS low (Note 7) 5
5
Output disable time after /CAS high
(Note 12) 0 13
0 15
Output disable time after /OE high
(Note 12) 0 13
0 15
ns
ns
ns
ns
ns
ns
ns
ns
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a /RAS clock such as /RAS-Only refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for
measuring of output signals are 2.0(VOH)and 0.8(VOL).
8: Assumes that tRCD≥tRCD(max), tASC≥tASC(max) and tCP≥tCP(max).
9: Assumes that tRCD≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in
this table,tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD≥tRAD(max) and tASC≤tASC(max).
11: Assumes that tCP≤tCP(max) and tASC≥tASC(max).
12: tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT≤ I ±10uAI) and
is not reference to VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Symbol
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT
Parameter
Refresh cycle time
/RAS high pulse width
Delay time, /RAS low to /CAS low
(Note15)
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low (Note16)
Row address setup time before /RAS low
Column address setup time before /CAS low (Note17)
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
(Note18)
(Note18)
Delay time, /CAS high to data
(Note19)
Delay time, /OE high to data
(Note19)
Transition time
(Note20)
Limits
-5,-5S
-6,-6S
Min Max Min Max
64 64
30 40
18 37 20 45
5 10
00
10 10
13 25 15 30
00
0 5 0 10
8 10
13 15
00
00
13 15
13 15
1 50
1 50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.VIH(min) and VIL(max) of the switching characteristics
are 2.0V and 0.8V respectively.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than
tRCD(max), access time is controlled exclusively by tCAC or tAA.tRCD(min) is specified as tRCD(min)=tRAH(min)+2tT+tASC(min) .
16: tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by
tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
MIT-DS-0072-0.5
MITSUBISHI
ELECTRIC
( 11 / 25 )
26/Feb./1997
11 Page | ||
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| PDF Descargar | [ Datasheet MH4V64AXJJ-6S.PDF ] | |
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