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PDF MH32V725BST-5 Data sheet ( Hoja de datos )
| Número de pieza | MH32V725BST-5 | |
| Descripción | HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
MITSUBISHI LSIs
MH32V725BST -5, -6
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH32V725BST is 33554432-word x 72-bit dynamic
ram stacked structural module. This consist of thirty-six
industry standard 16M x 4 dynamic RAMs in TSOP and
two industry standard input buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
MH32V725BST-5 50 19 30 19 84 12.8
MH32V725BST-6 60 21 35 21 104 11
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 16M x 4 RAMs SOJ and industry
standard input buffer in TSSOP
168-pin (84-pin dual dual in-line package)
Single 3.3V(± 0.3V) supply operation
Low stand-by power dissipation . . . . . . . . . . 135.7mW(Max)
Low operation power dissipation
MH32V725BST -5 . . . . . . . . . . . . . . . . . . 14.96W(Max)
MH32V725BST -6 . . . . . . . . . . . . . . . . . . 13.66W(Max)
All input are directly LVTTL compatible
All output are three-state and directry LVTTL compatible
Includes(0.22 uF x 38) decoupling capacitors
4096 refresh cycle every 64ms (CBR Ref)
8192 refresh cycle every 64ms (RAS Only Ref,Normal R/W)
Hyper-page mpde,Read-modify-write,/CAS before /RAS refresh,
Hidden refresh capabilities
JEDEC standard pin configration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
BACK SIDE
124pin 40pin
125pin 41pin
FRONT SIDE
APPLICATION
Main memory unit for computers , Microcomputer memory
PD&ID TABLE
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1
-5 1 0 0 0 1 0 0 0 0 0
-6 1 0 0 0 1 1 1 0 0 0
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
1 MIT - DS - 0237-0.0
MITSUBISHI
ELECTRIC
168pin 84pin
27/Jul./1998
1 page  
Preliminary Spec.
MITSUBISHI LSIs
MH32V725BST -5, -6
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply voltage
IO Output current
Pd Power dissipation
Topr
Operating temperature
Tstg Storage temperature
Conditions
With respect to Vss
Ta=25°C
Ratings
-0.5~4.6
50
38
0~70
-40~125
Unit
V
mA
W
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Vcc Supply voltage
Vss Supply voltage
VIH High-level input voltage, all inputs
VIL Low-level input voltage
Note 1 : All voltage values are with respect to Vss
(Ta=0~70°C, unless otherwise noted) (Note 1)
Limits
Min Nom Max
3.0 3.3 3.6
00
0
2.0 Vcc+0.3
-0.3 0.8
Unit
V
V
V
V
ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V +/- 0.3V, Vss=0V, unless otherwise noted) (Note 2)
Symbol
Parameter
Test conditions
Limits
Min Typ
VOH
High-level output voltage
IOH=-2.0mA
2.4
VOL
IOZ
II
Low-level output voltage
Off-state output current
Input current (except /RAS)
IOL=2.0mA
Q floating 0V VOUT Vcc
0V VIN Vcc+0.3V, Other input pins=0V
0
-20
-1
I I (RAS) Input current (/RAS)
0V VIN Vcc+0.3V, Other input pins=0V -90
Average supply
ICC1 (AV)
current
from Vcc operating
-5
(Note 3,4,5) - 6
/RAS, /CAS cycling
tRC=tWC=min.
output open
ICC2
Supply current from Vcc , stand-by
/RAS=/CAS =VIH, output open
/RAS=/CAS Vcc -0.2, output open
ICC4(AV)
Average supply current
from Vcc
Hyper-Page-Mode
(Note 3,4,5)
-5
-6
/RAS=VIL,/CAS cycling
tPC=min.
output open
ICC6(AV)
Average supply current from Vcc
/CAS before /RAS refresh
mode
(Note 3,5)
-5
-6
/CAS before /RAS refresh cycling
tRC=min.
output open
Max
Vcc
0.4
20
1
90
1825
1645
43
25
1825
1645
4687
4327
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VIH
Unit
V
V
uA
uA
uA
mA
mA
mA
mA
CAPACITANCE (Ta = 0~70°C, Vcc = 3.3V +/- 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
CI (/RAS) Input capacitance, /RAS input
CI Input capacitance, except /RAS input
C(DQ) Input/Output capacitance,DATA
Test conditions
VI=Vss
f=1MHZ
Vi=25mVrms
Limits
Min Typ Max
78
21
29
Unit
pF
pF
pF
5 MIT - DS - 0237-0.0
MITSUBISHI
ELECTRIC
27/Jul./1998
5 Page 
Preliminary Spec.
MITSUBISHI LSIs
MH32V725BST -5, -6
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
Delayed Write Cycle
/RAS
VIH
VIL
/ CAS
VIH
VIL
A0,B0~A12
VIH
VIL
VIH
/W
VIL
DQ
(INPUTS)
VIH
VIL
DQ
(OUTPUTS)
VOH
VOL
VIH
/OE
VIL
tWC
tRAS
tRP
tCRP
tRCD
tCSH
tRSH
tCAS
tCRP
tASR
tRAH
ROW
ADDRESS
tASC
tRCS
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWP
tDZC
Hi-Z
tCLZ
tWCH
tDS tDH
DATA
VALID
tASR
ROW
ADDRESS
Hi-Z
tDZO
tOEZ
tODD
tOEH
Hi-Z
11 MIT - DS - 0237-0.0
MITSUBISHI
ELECTRIC
27/Jul./1998
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MH32V725BST-5.PDF ] | |
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