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PDF PHP14NQ20T Data sheet ( Hoja de datos )

Número de pieza PHP14NQ20T
Descripción TrenchMOS transistor
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors
TrenchMOStransistor
Product specification
PHP14NQ20T, PHB14NQ20T
FEATURES
’Trench’ technology
• Low on-state resistance
• Fast switching
• High thermal cycling performance
• Low thermal resistance
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 200 V
ID = 14 A
RDS(ON) 230 m
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology. The device
has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications.
The PHP14NQ20T is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB14NQ20T is supplied in the SOT404 (D2PAK) surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
tab
tab
2 drain1
3 source
tab drain
1 23
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 k
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
200
200
± 20
14
10
56
125
175
UNIT
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 package
October 1999
1
Rev 1.000

1 page




PHP14NQ20T pdf
Philips Semiconductors
TrenchMOStransistor
Product specification
PHP14NQ20T, PHB14NQ20T
Drain current, ID (A)
28
24
20
16
12 Tj = 25 C
175 C
8
4
0
0 2 4 6 8 10
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Transconductance, gfs (S)
20
15
10
5
0
0 4 8 12 16 20 24 28
ID / (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
3a
Rds(on) normalised to 25degC
2.5
2
1.5
1
0.5
-100
-50
0 50 100 150 200
Tmb / degC
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 7 A; VGS = 10 V
VGS(TO) / V
5
max.
4
typ.
3
min.
2
BUK759-60
1
-0100
-50
0 50
Tj / C
100 150 200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2% typ
98%
1E-04
1E-05
1E-06
01234
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
5
Capacitances, Ciss, Coss, Crss (pF)
10000
1000
100
Ciss
Coss
Crss
10
0
10 20 30
Drain-Source Voltage, VDS (V)
40
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
October 1999
5
Rev 1.000

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