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PDF PHN1015 Data sheet ( Hoja de datos )
| Número de pieza | PHN1015 | |
| Descripción | N-channel TrenchMOS transistor Logic level | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors
N-channel TrenchMOS transistor
Logic level
Product specification
PHN1015
FEATURES
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• Low-profile surface mount
package
• Logic level compatible
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 25 V
ID = 10 A
RDS(ON) ≤ 15 mΩ (VGS = 10 V)
RDS(ON) ≤ 18 mΩ (VGS = 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a surface mounting
plastic package using ’trench’
technology.
Application:-
• High frequency computer
motherboard d.c. to d.c. converters
The PHN1015 is supplied in the
SOT96-1 (SO8) surface mounting
package.
PINNING
PIN DESCRIPTION
1-3 source
4 gate
5-8 drain
SOT96-1 (SO8)
876 5
pin 1 index
1 23
4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
Ptot
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse peak
value)
Drain current (tp ≤ 10 s)
Drain current (pulse peak value)
Total power dissipation
Operating junction and storage
temperature
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C;
RGS = 20 kΩ
-
Ta = 25 ˚C
Ta = 70 ˚C
Ta = 25 ˚C
Ta = 25 ˚C
Ta = 70 ˚C
-
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
± 15
± 20
10
8
40
2.5
1.6
150
UNIT
V
V
V
V
A
A
A
W
W
˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-a
Rth j-a
Thermal resistance junction
to ambient
Thermal resistance junction
to ambient
CONDITIONS
Surface mounted, FR4 board, t ≤ 10 sec
Surface mounted, FR4 board
TYP.
-
150
MAX.
50
-
UNIT
K/W
K/W
December 1999
1
Rev 1.300
1 page  
Philips Semiconductors
N-channel TrenchMOS transistor
Logic level FET
Product specification
PHN1015
Gate-source voltage, VGS (V)
15
14 ID = 10A
13 Tj = 25 C
12
11 VDD = 15 V
10
9
8
7
6
5
4
3
2
1
0
0 5 10 15 20 25 30 35 40 45 50
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Source-Drain Diode Current, IF (A)
50
VGS = 0 V
45
40
35
30 150 C
25
Tj = 25 C
20
15
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
December 1999
5
Rev 1.300
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PHN1015.PDF ] | |
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