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PDF MC10EP105FA Data sheet ( Hoja de datos )
| Número de pieza | MC10EP105FA | |
| Descripción | Quad 2-Input Differential AND/NAND | |
| Fabricantes | ON Semiconductor | |
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MC10EP105
Product Preview
Quad 2-Input Differential
AND/NAND
The MC10EP105 is a 2–input differential AND/NAND gate. Each
gate is functionally equivalent to a EP05 and LVEL05 devices. With
AC performance much faster than the LVEL05 device, the EP105 is
ideal for applications requiring the fastest AC performance available.
All VCC and VEE pins must be externally connected to power supply to
guarantee proper operation.
• 190ps Typical Propagation Delay
• High Bandwidth to 3 Ghz Typical
• ECL mode: 0V VCC with VEE = –3.0V to –5.5V
• PECL mode: 3.0V to 5.5V VCC with VEE = 0V
• Internal Input Pulldown Resistors
• ESD Protection: >2KV HBM, >100V MM
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 444 devices
LOGIC DIAGRAM
D0a
D0a
Q0
D0b
D0b
Q0
D1a
D1a
Q1
D1b
D1b
Q1
D2a
D2a
Q2
D2b
D2b
Q2
D3a
D3a
Q3
D3b
D3b
Q3
http://onsemi.com
32–LEAD TQFP
FA SUFFIX
CASE 873A
MARKING DIAGRAM*
MC10
EP105
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
32
1
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN FUNCTION
Dna, Dnb, Dna, Dnb
ECL Data Inputs
Qn, Qn
ECL Data Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative, 0 Supply
TRUTH TABLE
Dna Dnb Dna Dnb Qn Qn
L L HH L H
L HHL L H
H LLH LH
H
HL
L
HL
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 0
1
ORDERING INFORMATION
Device
Package
Shipping
MC10EP105FA
TQFP 250 Units/Tray
MC10EP105FAR2 TQFP 2000 Tape & Reel
Publication Order Number:
MC10EP105/D
1 page  
MC10EP105
PACKAGE DIMENSIONS
TQFP
FA SUFFIX
32–LEAD PLASTIC PACKAGE
CASE 873A–02
ISSUE A
A1
32
A
4X
0.20 (0.008) AB T–U Z
25
1
–T–
B
B1
8
9
DETAIL Y
–U–
V
17 V1
9
–Z– 4X
S1 0.20 (0.008) AC T–U Z
S
–AB–
SEATING
PLANE
–AC–
G
0.10 (0.004) AC
8X M_
CE
R
DETAIL AD
BASE
METAL
FÉÉÉÉJNÉÉÉÉ D
SECTION AE–AE
W
H
K
X
Q_
DETAIL AD
AE
P
DETAIL Y
AE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE
DETERMINED AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL
BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
MILLIMETERS
DIM MIN MAX
A 7.000 BSC
A1 3.500 BSC
B 7.000 BSC
B1 3.500 BSC
C 1.400 1.600
D 0.300 0.450
E 1.350 1.450
F 0.300 0.400
G 0.800 BSC
H 0.050 0.150
J 0.090 0.200
K 0.500 0.700
M 12_ REF
N 0.090 0.160
P 0.400 BSC
Q 1_ 5_
R 0.150 0.250
S 9.000 BSC
S1 4.500 BSC
V 9.000 BSC
V1 4.500 BSC
W 0.200 REF
X 1.000 REF
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055 0.063
0.012 0.018
0.053 0.057
0.012 0.016
0.031 BSC
0.002 0.006
0.004 0.008
0.020 0.028
12_ REF
0.004 0.006
0.016 BSC
1_ 5 _
0.006 0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
http://onsemi.com
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