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PDF MC100LVEL37 Data sheet ( Hoja de datos )
| Número de pieza | MC100LVEL37 | |
| Descripción | Clock Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC100LVEL37
3.3 V ECL 1:4 ÷1/÷2 Clock
Fanout Buffer
Description
The MC100LVEL37 is a fully differential 1:4 fanout buffer. The
device offers two outputs at ÷1 of the input frequency, and two outputs
at ÷2 of the input frequency. The Low Output-Output Skew of the
device makes it ideal for distributing 1x and 1/2x frequency
synchronous signals.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the CLKn input will pull down to VEE, The CLKn input
will bias around VCC/2 and the Qn output will go LOW.
Features
• 700 ps Typical Propagation Delays
• 50 ps Maximum Output-Output Skews
• ESD Protection:
♦ > 2 kV Human Body Model
♦ > 200 V Machine Model
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: VCC = 3.0 V to 3.8 V
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Qn Output will Default LOW with Inputs Open or at VEE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity: Level 3 (Pb-Free)
(For Additional Information, see Application Note AND8003/D)
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index 28 to 34
• Transistor Count = 256 Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
SOIC−20 WB
DW SUFFIX
CASE 751D−05
MARKING DIAGRAM*
20
100LVEL37
AWLYYWWG
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package Shipping†
MC100LVEL37DWG
SOIC−20 WB 38 Units / Tube
(Pb-Free)
MC100LVEL37DWR2G SOIC−20 WB 1000Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 7
1
Publication Order Number:
MC100LVEL37/D
1 page  
MC100LVEL37
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
www.onsemi.com
5
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC100LVEL37.PDF ] | |
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