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PDF LMX2353 Data sheet ( Hoja de datos )
| Número de pieza | LMX2353 | |
| Descripción | PLLatinum Fractional N Single 2.5 GHz Frequency Synthesizer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
June 1999
LMX2353
PLLatinum™ Fractional N Single 2.5 GHz Frequency
Synthesizer
General Description
The LMX2353 is a monolithic integrated fractional N fre-
quency synthesizer, designed to be used in a local oscillator
subsystem for a radio transceiver. It is fabricated using Na-
tional’s 0.5µ ABiC V silicon BiCMOS process. The LMX2353
contains dual modulus prescalers along with modulo 15 or
16 fractional compensation circuitry in the N divider. A 16/17
or 32/33 prescale ratio can be selected for the LMX2353. Us-
ing a fractional N phase locked loop technique, the LMX2353
can generate very stable low noise control signals for UHF
and VHF voltage controlled oscillators (VCO’s).
The LMX2353 has a highly flexible 16 level programmable
charge pump supplies output current magnitudes from 100
µA to 1.6 mA. Serial data is transferred into the LMX2353 via
a three wire interface (Data, LE, Clock). Supply voltage can
range from 2.7V to 5.5V. The LMX2353 features very low
current consumption; typically 4.5 mA at 3.0V. The LMX2353
is available in a 16-pin TSSOP or a 16-pad CSP surface
mount plastic package.
Features
n 2.7V – 5.5V operation
n Low Current Consumption
ICC = 4.5 mA typ @ VCC = 3.0V
n Programmable or Logical Power Down Mode
ICC = 5 µA typ @ VCC = 3.0V
n Modulo 15 or 16 fractional N divider
Supports ratios of 1, 2, 3, 4, 5, 8, 15, or 16
n Programmable charge pump current levels
100 µA to 1.6 mA in 100 µA steps
n Digital Filtered Lock Detect
Applications
n Portable wireless communications (PCS/PCN, cordless)
n Zero blind slot TDMA systems
n Cellular and Cordless telephone systems
n Spread spectrum communication systems (CDMA)
Functional Block Diagram
MICROWIRE™ and PLLatinum™ are trademarks of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS101124
DS101124-1
www.national.com
1 page  
1.0 Functional Description (Continued)
1.3.2 Fractional Compensation
The fractional compensation circuitry in the N divider allows the user to adjust the VCO’s tuning resolution in 1/16 or 1/15 incre-
ments of the phase detector comparison frequency. A 4-bit register is programmed with the fractions desired numerator, while an-
other bit selects between fractional 15 and 16 modulo base denominator. An integer average is accomplished by using a 4-bit ac-
cumulator. A variable phase delay stage compensates for the accumulated integer phase error, minimizing the charge pump duty
cycle, and reducing spurious levels. This technique eliminates the need for compensation current injection in to the loop filter.
Overflow signals generated by the accumulator are equivalent to 1 full VCO cycle, and result in a pulse swallow.
1.4 PHASE/FREQUENCY DETECTOR
The phase/frequency detector is driven from the N and R counter outputs. The maximum frequency at the phase detector input
is about 2 MHz for some high frequency VCO due to the minimum continuous divide ratio of the dual modulus prescaler. For ex-
ample, if the VCO output frequency is 1.984 GHz, the maximum phase detector input frequency is 2 MHz because the minimum
continuous divide ratio with 32/33 prescaler is 1056. The phase detector outputs control the charge pumps. The polarity of the
pump-up or pump-down control is programmed using PD_POL depending on whether the VCO characteristics are positive or
negative. The phase detector also receives a feedback signal from the charge pump, in order to eliminate dead zone.
1.5 CHARGE PUMPS
The phase detector’s current source output pumps charge into an external loop filter, which then integrates into the VCO’s control
voltage. The charge pump steers the charge pump output CPo to VCC (pump-up) or Ground (pump-down). When locked, CPo is
primarily in a TRI-STATE mode with small corrections. The charge pump output current magnitude can be selected from 100 µA
to 1.6 mA by programming the CP_WORD bits.
1.6 VOLTAGE DOUBLER
The Vp pin is normally driven from an external power supply over a range of VCC to 5.5V to provide current for the RF charge
pump circuit. An internal voltage doubler circuit connected between the VCC and Vp supply pins alternately allows VCC = 3V
(±10%) users to run the RF charge pump circuit at close to twice the VCC power supply voltage. The Voltage doubler mode is en-
abled by setting the V2_EN bit (R[20]) to a HIGH level. The average delivery current of the doubler is less than the instantaneous
current demand of the RF charge pump when active and is thus not capable of sustaining a continuous out of lock condition. A
large external capacitor connected to Vp (≈ 0.1 µF) is therefore needed to control power supply droop when changing frequencies.
1.7 MICROWIRE™ SERIAL INTERFACE
The programmable functions are accessed through the MICROWIRE serial interface. The interface is made of three functions:
clock, data and latch enable (LE). Serial data for the various counters is clocked in from data on the rising edge of clock, into the
24-bit shift register. Data is entered MSB first. The last two bits decode the internal register address. On the rising edge of LE,
data stored in the shift register is loaded into one of the 4 appropriate latches (selected by address bits). A complete programming
description is included in the following sections.
1.8 Lock Detect Output
A digital filtered lock detect function is included with each phase detector through an internal digital filter to produce a logic level
output available on the FoLD output pin if selected. The lock detect output is high when the error between the phase detector in-
puts is less than 15 ns for 5 consecutive comparison cycles. The lock detect output is low when the error between the phase de-
tector inputs is more than 30 ns for one comparison cycle. An analog lock detect status generated from the phase detector is also
available on the FoLD output pin, if selected. The lock detect output goes high when the charge pump is inactive. It goes low when
the charge pump is active during a comparison cycle. When a PLL is in power down mode, the respective lock detect output is
always low.
1.9 OUT0/OUT1 Output Modes (Fastlock & CMOS Output Modes)
The OUT_0 and OUT_1 pins are normally used as general purpose CMOS outputs or as part of a fastlock scheme. There is also
a production test mode that overrides the other two normal modes when activated. The selection of these modes is determined
by the 4 bit CMOS register (F2_15–18) described in Table 2.5.3.
The fastlock mode allows the user to open up the loop bandwidth momentarily while acquiring lock by increasing the charge pump
output current magnitude while simultaneously switching in a second resistor element to ground via the OUT0 output pin. The
loop will lock faster without any additional stability considerations as the phase margin remains constant.
The loop bandwidth during fastlock can be opened up by as much as a factor of 4. The amount of bandwidth increase is a function
of the square root of the charge pump current increase. The maximum charge pump current ratio results from switching the
charge pump current between 100 µA and 1.6 mA. The damping resistor ratio for these two charge pump current setting changes
by the reciprocal of the bandwidth change. In the 4 to 1 bandwidth scenerio, the resulting damping resistor value would be 1/4th
of the steady state value. This would be achieved by switching 3 more identical resistors in parallel with the first to ground through
the OUT_0 pin.
5 www.national.com
5 Page 
2.0 Programming Description (Continued)
R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual modulus prescaler (P = 16 or 32)
2.4 F1 REGISTER
If the ADDRESS[1:0] field is set to 0 0, data is transferred from the 24-bit shift register into the F1 register when Latch Enable (LE)
signal goes high . The F1 register sets the fractional divider denominator FRAC_16 bit and Fout/ Lock Dectect output FoLD word.
The rest of the bits F1_0 - F1_16, and F1_21 are Don’t Care.
Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
Data Field
Address Field
0 FRAC
_16
FoLD
These bits should be set to zero
F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1
_21 _20 _19 _18 _17 _16 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
0
0
Note:0 denotes setting the bit to zero.
2.4.1 FRAC_16
The FRAC_16 bit is used to set the fractional compensation at either 1/16 or 1/15 resolution. When FRAC_16 bit is set to one,
the fractional modulus is set to 1/16 resolution, and FRAC_16 = 0 corresponds to 1/15. See section 2.3.5 for fractional divider
values.
Bit Location
Function
01
FRAC_16
F1_20
Fractional Modulus 1/15 1/16
2.4.2 FoLD
The FoLD word is used to set the function of the Lock Detect output pin according to the Table 2.4.2.1 below. Open drain lock de-
tect output is provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is se-
lected, the pin is HIGH, with narrow pulses LOW. See typical Lock detect timing in section 2.4.2.4.
2.4.2.1 FOLD Programming Truth Table
F1_19
F1_18
00
00
01
01
10
10
11
11
Reserved - Denotes a disallowed programming condition.
F1_17
0
1
0
1
0
1
0
1
FoLD Output State
Analog Lock Detect
(Open Drain)
Reserved
Digital Lock Detect
Reserved
Reserved
Reserved
N Divider Output
R Divider Output
2.4.2.2 Lock Detect (LD) Digital Filter
The LD Digital Filter compares the difference between the phase of the inputs of the phase detector to a RC generated delay of
approximately 15 ns. To enter the locked state (Lock = HIGH) the phase error must be less than the 15 ns RC delay for 5 con-
secutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately 30 ns. To exit the locked state
(Lock = LOW), the phase error must become greater than the 30 ns RC delay. If the PLL is unlocked, the lock detect output will
be forced LOW. A flow chart of the digital filter is shown next.
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LMX2353.PDF ] | |
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