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PDF LMS485EINA Data sheet ( Hoja de datos )
| Número de pieza | LMS485EINA | |
| Descripción | Low Power RS-485 / RS-422 Differential Bus Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 2003
LMS485E
Low Power RS-485 / RS-422 Differential Bus Transceiver
General Description
The LMS485E is a low power differential bus/line transceiver
designed for high speed bidirectional data communication on
multipoint bus transmission lines. It is designed for balanced
transmission lines. It meets ANSI Standards TIA/EIA
RS422-B, TIA/EIA RS485-A and ITU recommendation and
V.11 and X.27. The driver outputs and receiver inputs have
±15kV ESD protection. The LMS485E combines a TRI-
STATE™ differential line driver and differential input receiver,
both of which operate from a single 5.0V power supply. The
driver and receiver have an active high and active low,
respectively, that can be externally connected to function as
a direction control. The driver outputs and receiver inputs are
internally connected to form a differential input/output (I/O)
bus port that is designed to offer minimum loading to bus
whenever the driver is disabled or when VCC = 0V. These
ports feature wide positive and negative common mode
voltage ranges, making the device suitable for multipoint
applications in noisy environments. The LMS485E is avail-
able in 8-Pin SOIC and 8-pin DIP packages. It is a drop-in
replacement to Maxim’s MAX485E.
Features
n Meet ANSI standard RS-485 and RS-422
n Data rate 2.5 Mbps
n Single supply voltage operation, 5V
n Wide input and output voltage range
n Thermal shutdown protection
n Short circuit protection
n Low quiescent current 800µA (max)
n Allows up to 32 transceivers on the bus
n Open circuit fail-safe for receiver
n Extended operating temperature range −40˚C to 85˚C
n Drop-in replacement to MAX485E
n Available in 8-pin SOIC and 8-pin DIP packages
Applications
n Low power RS-485 systems
n Network hubs, bridges, and routers
n Point of sales equipment (ATM, barcode scanners,…)
n Local area networks (LAN)
n Integrated service digital network (ISDN)
n Industrial programmable logic controllers
n High speed parallel and serial applications
n Multipoint applications with noisy environment
Typical Application
20086601
A typical multipoint application is shown in the above figure. Terminating resistor, RT are typically required but only located at the two ends of the cable.
Pull-up and pull-down resistors maybe required at the end of the bus to provide fail-safe biasing. The biasing resistors provide a bias to the cable when all
drivers are in TRI-STATE, See National Application Note, AN-847 for further information.
© 2003 National Semiconductor Corporation DS200866
www.national.com
1 page  
Electrical Characteristics (Continued)
Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min Typ
VOL
CMOS Low-level Output
IOL = −4 mA, VID = 200 mV
Voltage
IOZR
Tristate Output Leakage
Current
0.4V ≤ VO ≤ + 2.4V
RIN Input Resistance
Power Supply Current
− 7V ≤VCM ≤ +12V
12
ICC
IOSD1
Supply Current
Driver Short-circuit Output
Current
DE = VCC, RE = GND or VCC
DE = 0V, RE = GND or VCC
VO = high, −7V ≤ VCM ≤ +12V
400
360
IOSD2
Driver Short-circuit Output
Current
VO = low, − 7V ≤VCM ≤ +12V
IOSR
Receiver Short-circuit Output 0 V ≤ VO ≤ VCC
Current
Switching Characteristics
Driver
TPLH,
TPHL
TSKEW
TR,
TF
TZH,
TZL
THZ,
TLZ
Receiver
Propagation Delay Input to
Output
Driver Output Skew
Driver Rise and Fall Time
Driver Enable to Ouput Valid
Time
Driver Output Disable Time
RL = 54Ω, CL = 100 pF
RL = 54Ω, CL = 100 pF
RL = 54Ω, CL = 100 pF
CL = 100 pF
CL = 15 pF
10 40
5
3 10
25
35
TPLH,
TPHL
TSKEW
TZH,
TZL
THZ,
TLZ
FMAX
Propagation Delay Input to
Output
Receiver Output Skew
Receiver Enable Time
Receiver Disable Time
Maximum Data Rate
RL = 54Ω, CL = 100 pF
RL = 54Ω, CL = 100 pF
CL = 15 pF
CL = 15 pF
20 90
5
20
20
2.5
Max
0.4
±1
800
560
250
250
95
80
10
40
70
70
200
50
50
Units
V
µA
kΩ
µA
mA
mA
mA
ns
ns
ns
ns
ns
ns
ns
ns
ns
Mbps
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: All voltage values, except differential I/O bus voltage, are with respect to the network ground terminal.
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature, TA, is
PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Note 4: ESD rating based upon human body model, 100 pF discharged through 1.5 kΩ.
Note 5: Voltage limits apply to DI, DE, RE pins.
Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B.
Note 7: |∆VOD| and |∆VOC| are changes in magnitude of VOD and VOC, respectively when the input changes from high to low levels.
Note 8: Peak current
5 www.national.com
5 Page 
Application Information
POWER LINE NOISE FILTERING
A factor to consider in designing power and ground is noise
filtering. A noise filtering circuit is designed to prevent noise
generated by the integrated circuit (IC) as well as noise
entering the IC from other devices. A common filtering
method is to place by-pass capacitors (Cbp) between the
power and ground lines.
Placing a by-pass capacitor (Cbp) with the correct value at
the proper location solves many power supply noise prob-
lems. Choosing the correct capacitor value is based upon
the desired noise filtering range. Since capacitors are not
ideal, they may act more like inductors or resistors over a
specific frequency range. Thus, many times two by-pass
capacitors may be used to filter a wider bandwidth of noise.
It is highly recommended to place a larger capacitor, such as
10µF, between the power supply pin and ground to filter out
low frequencies and a 0.1µF to filter out high frequencies.
By-pass capacitors must be mounted as close as possible to
the IC to be effective. Longs leads produce higher imped-
ance at higher frequencies due to stray inductance. Thus,
this will reduce the by-pass capacitor’s effectiveness. Sur-
face mounted chip capacitors are the best solution because
they have lower inductance.
20086622
FIGURE 11. Placement of by-pass Capacitors, Cbp
11 www.national.com
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