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PDF Am29LV002T-150ECB Data sheet ( Hoja de datos )
| Número de pieza | Am29LV002T-150ECB | |
| Descripción | 2 Megabit (256 K x 8-Bit) CMOS 3.0 Volt-only/ Boot Sector Flash Memory | |
| Fabricantes | AMD | |
| Logotipo |  |
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PRELIMINARY
Am29LV002
2 Megabit (256 K x 8-Bit)
CMOS 3.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors
s High performance
— Full voltage range: access times as fast as 100
ns
— Regulated voltage range: access times as fast
as 90 ns
s Ultra low power consumption (typical values at
5 MHz)
— Automatic Sleep Mode: 200 nA
— Standby mode: 200 nA
— Read mode: 10 mA
— Program/erase mode: 20 mA
s Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
— Supports control code and data storage on a
single device
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s Top or bottom boot block configurations
available
s Embedded Algorithms
— Embedded Erase algorithms automatically
preprogram and erase the entire chip or any
combination of designated sectors
— Embedded Program algorithms automatically
write and verify bytes or words at specified
addresses
s Typical 1,000,000 write cycles per sector
(100,000 cycles minimum guaranteed)
s Package option
— 40-pin TSOP
s Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
s Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
s Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
s Erase Suspend/Erase Resume feature
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s Hardware reset pin (RESET#)
— Hardware method to reset the device to the read
mode
Publication# 21191 Rev: C Amendment/+2
Issue Date: March 1998
.
1
1 page  
PRELIMINARY
PIN CONFIGURATION
A0–A17 = 18 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
WE#
= Write enable
OE#
= Output enable
RESET# = Reset pin
RY/BY# = Ready/Busy# pin
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS = Device ground
NC = Pin not connected internally
LOGIC SYMBOL
18
A0–A17
DQ0–DQ7
CE#
OE#
WE#
RESET#
RY/BY#
8
21191C-3
Am29LV002
5
5 Page 
PRELIMINARY
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.
The system must issue the reset command to re-ena-
ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
See “AC Characteristics” for parameters, and to Figure
13 for the timing diagram.
Am29LV002
11
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| PDF Descargar | [ Datasheet Am29LV002T-150ECB.PDF ] | |
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