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PDF SL74HC4015D Data sheet ( Hoja de datos )

Número de pieza SL74HC4015D
Descripción Dual 4-Bit Shift Register
Fabricantes System Logic Semiconductor 
Logotipo System Logic Semiconductor Logotipo



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No Preview Available ! SL74HC4015D Hoja de datos, Descripción, Manual

SL74HC4015
Dual 4-Bit Shift Register
High-Performance Silicon-Gate CMOS
The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two identical independent 4-stage serial-
input/parallel-output registers. Each register has independent Clock
and Reset inputs as well as a single serial Data input. “Q” outputs are
available from each of the four stages on both registers. All register
stages are D-type, master-slave flip-flops. The logic level present at the
Data input is transferred into the first register stage and shifted over
one stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC4015N Plastic
SL74HC4015D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 = VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Clock Data
L
H
X
XX
* = No Change
X = don’t care
Reset
L
L
L
H
Outputs
Q0 Qn
L Qn-1
H Qn-1
Q0* Qn*
LL
SLS
System Logic
Semiconductor

1 page




SL74HC4015D pdf
SL74HC4015
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
SLS
System Logic
Semiconductor

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