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PDF SMP402SC Data sheet ( Hoja de datos )
| Número de pieza | SMP402SC | |
| Descripción | 20-72 VDC Input Non-isolated DC Output | |
| Fabricantes | Power Integrations Inc. | |
| Logotipo |  |
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SMP402
1-Watt Buck Regulator IC
20-72 VDC Input
Non-isolated DC Output
Product Highlights
Integrated Power Switch and CMOS Controller
• Output power > 1 W from 48 VDC input
• Adjustable output voltage
• Integrated solution minimizes overall size
High-voltage, Low-capacitance MOSFET Output
• Designed for ISDN T1 telecommunications applications
• Low capacitance allows for high frequency operation
+
48 VDC
-
High-voltage Buck Regulator
• Internal pre-regulator self-powers the IC on start-up
• Designed for low power consumption
• Minimum external parts required
Built-In Self-protection Circuits
• Undervoltage lockout
• Thermal shutdown
• Input polarity/level sense
SMP402
Figure 1. Typical Application.
®
+
5 VDC
-
PI-555A-123091
Description
The SMP402, intended for non-isolated ISDN
telecommunications power supply applications, combines a
high voltage power MOSFET switch with a switchmode power
system controller in a monolithic integrated circuit. Few
external components are required to implement a low cost
power supply which meets stringent ISDN specifications. High
frequency operation reduces total power supply size.
The P-channel power MOSFET switch features include high
voltage, low R , and low capacitance. Lower capacitance
DS(ON)
results in a reduction in gate drive power, and also facilitates
higher frequency operation.
The controller section of the SMP402 contains all the blocks
required to drive and control the power stage: start-up pre-
regulator circuit, oscillator, bandgap reference, error amplifier,
gate driver and level shift. Protection features include
undervoltage lockout, thermal shutdown, and input polarity
and level sensing.
The SMP402 is available in a 16-pin plastic SOIC package.
VIN
VLS
ENABLE
D GND
A GND
SENSE+
SENSE -
REXT
1
2
3
4
5
6
7
8
Figure 2. Pin Configuration.
16 OUT
15 POLARITY
14 LEVEL
13 VS
12 EA IN
11 EA OUT
10 VBIAS
9 CEXT
PI-553B-012892
ORDERING INFORMATION
PART
NUMBER
SMP402SC
PACKAGE
OUTLINE
S16A
T
j
RANGE
0 to 120°C
January 1996
1 page  
Functional Description (cont.)
POLARITY current threshold.
Regulation of the output voltage is
detected by a comparator which looks
for error amplifier saturation in the output
high (maximum duty cycle) state.
Power supply turn on and turn off with a
slowly changing input voltage is shown
in Figure 4 as measured using the circuit
shown in Figure 6. Also shown are the
level and polarity outputs. The input
voltage must rise above 32 V before the
SMP402 will turn on. At this input
voltage the current through R1 into the
SENSE+ input exceeds the threshold
current (typically 23 µA), the LEVEL
and POLARITY outputs go high, and
the power supply turns on. As the input
voltage goes down, LEVEL will go low
at approximately 30 V, but POLARITY
will stay high. As the input voltage
continues to drop, POLARITY goes low
at approximately 12 V and the converter
loses regulation at approximately 10 V
and turns off. The LEVEL output will
go high and the power supply turns on
when the input voltage reaches -32 V.
POLARITY stays low to indicate that
the input voltage has reversed polarity.
As the negative input voltage falls toward
zero, LEVEL goes low at approximately
-30 V and the converter loses regulation
and turns off at approximately -10 V.
SMP402
Enable
The power supply can be shut down by
pulling the ENABLE pin low. It is
internally pulled up to VS with a 100 µA
(nominal) current source. However, it is
recommended that this pin be tied to V
S
if it is unused.
P-Channel Output Transistor
The output MOSFET is a 90 V pass
transistor capable of supplying >200
mA. To minimize switching noise and
EMI, it is important to keep the path
from OUT through the output diode, the
input storage capacitor, and into V as
IN
short as possible.
INPUT VOLTAGE CONDITION
Negative voltage, level too low
Negative voltage, correct level
Positive voltage, level too low
Positive voltage, correct level
POLARITY
0
0
1
1
LEVEL
0
1
0
1
Figure 5. LEVEL/POLARITY Truth Table. The LEVEL and POLARITY signals are only valid when the output voltage is in regulation.
5D
1/96
5 Page 
BREAKDOWN vs. TEMPERATURE
1.1
1.0
0.9
-50 -25 0 25 50 75 100 125 150
Junction Temperature (°C)
COSS vs. DRAIN VOLTAGE
100
80
60
40
20
0
0
20 40 60
Drain Voltage (V)
80
SMP402
fPWM vs. EXTERNAL CAPACITANCE
500
400
300
200
100
0
0
100 200 300 400
External Capacitance (pF)
500
DRAIN CHARGE vs. DRAIN VOLTAGE
3.0
2.5
2.0
1.5
1.0
0.5
0
0
20 40 60
Drain Voltage (V)
80
DRAIN CAPACITANCE ENERGY
60
50
40
30
20
10
0
0
20 40 60
Drain Voltage (V)
80
11D
1/96
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet SMP402SC.PDF ] | |
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