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PDF Si5110-BC Data sheet ( Hoja de datos )
| Número de pieza | Si5110-BC | |
| Descripción | SiPHY OC-48/STM-16 SONET/SDH TRANSCEIVER | |
| Fabricantes | Silicon Storage Technology Inc | |
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Si5110
PRELIMINARY DATA SHEET
SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER
Features
Complete low power, high speed, SONET/SDH transceiver with
integrated limiting amp, CDR, CMU, and MUX/DEMUX
Data Rates Supported:
OC-48/STM-16 and 2.7 Gbps FEC
SONET Compliant Loop Timed
Operation
Low Power Operation 1.0 W (typ)
Programmable Slicing Level and
DSPLL™ Based Clock Multiplier Unit Sample Phase Adjustment
w/ Selectable Loop Filter Bandwidths LVDS Parallel Interface
Integrated Limiting Amplifier
Single Supply 1.8 V Operation
Diagnostic and Line Loopbacks
11 x 11 mm BGA Package
Applications
Sonet/SDH Transmission
Systems
Optical Transceiver Modules
Sonet/SDH Test Equipment
Description
The Si5110 is a complete low-power transceiver for high-speed serial
communication systems operating between 2.5 Gbps and 2.7 Gbps. The receive
path consists of a fully integrated limiting amplifier, clock and data recovery unit
(CDR), and 1:4 deserializer. The transmit path combines a low jitter clock
multiplier unit (CMU) with a 4:1 serializer. The CMU uses Silicon Laboratories’
DSPLL™ technology to provide superior jitter performance while reducing design
complexity by eliminating external loop filter components. To simplify BER
optimization in long haul applications, programmable slicing, and sample phase
adjustment are supported.
The Si5110 operates from a single 1.8 V supply over the industrial temperature
range (–40°C to 85°C).
Functional Block Diagram
LOS
LOSLVL
PHASEADJ RXLO L
S L IC E L V L
LTR
RXSQLCH
RXDIN 2
Lim iting
AMP
CDR
8
REFSEL
REFCLK
LPTM
R E F R AT E
2
T XC LK 4 IN
2
÷2
TX LO L
BW SEL
D S PL L tm
TX CMU
TX C L K D S B L
TXCLKOUT
TXSQLCH
TX D O U T
2
2
÷2
2
8
RESET
RESET
Con trol
LLBK DLBK
FIFO ERR
TXM SBSEL
RXM SBSEL
R XD O U T[3:0
RXCLK1
RXCLK2
R X C L K 2 D IV
RXCLK2DSB
TX C LK 4O UT
T X C L K 4IN
T X D IN[3:0]
FIFO RST
Si5110
Bottom View
Ordering Information:
See page 23.
Preliminary Rev. 0.41 8/01
Copyright © 2001 by Silicon Laboratories
Si5110-DS041
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
1 page  
Si5110
All
Differential
IOs
tF
tR
Figure 3. I/O Rise/Fall Times
80%
20%
Table 2. DC Characteristics
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter
Supply Current
Power Dissipation
Voltage Reference (VREF)
Common Mode Input Voltage (RXDIN)
Differential Input Voltage Swing (RXDIN)
Symbol
IDD
PD
VREF
VICM
VID
Test Condition
VREF driving
10 kΩ load
See Figure 1
Min
—
—
1.21
TBD
10
Common Mode Output Voltage
(TXDOUT, TXCLKOUT)
Differential Output Voltage Swing
(TXDOUT, TXCLKOUT), Differential pk-pk
LVPECL Input Voltage HIGH (REFCLK)
LVPECL Input Voltage LOW (REFCLK)
LVPECL Input Voltage Swing,
Differential pk-pk (REFCLK)
LVPECL Internally Generated Input Bias
(REFCLK)
LVDS Input High Voltage (TXDIN,
TXCLK4IN)
LVDS Input Low Voltage (TXDIN, TXCLK4IN)
LVDS Input Voltage, Single Ended pk-pk
(TXDIN, TXCLK4IN)
LVDS Output High Voltage
(RXDOUT, RXCLK1, RXCLK2,
TXCLK4OUT)
LVDS Output Low Voltage
(RXDOUT, RXCLK1, RXCLK2,
TXCLK4OUT)
LVDS Output Voltage, Differential pk-pk
(RXDOUT, RXCLK1, RXCLK2,
TXCLK4OUT)
VOCM
VOD
VIH
VIL
VID
VIB
VIH
VIL
VISE
VOH1
VOL1
VOSE
See Figure 1
.8
800
Figure 1
1.975
1.32
250
1.6
—
0.0
100
100 Ω Load
Line-to-Line
100 Ω Load
Line-to-Line
100 Ω Load
Line-to-Line,
Figure 1
TBD
0.925
500
Typ
611
1.0
1.25
0.1
—
0.9
1000
2.3
1.6
—
1.95
—
—
—
—
—
—
Max
TBD
TBD
1.29
Unit
mA
W
V
TBD
1.0
1.0
V
mV
(pk-pk)
V
1200
2.59
1.99
2400
2.3
mV
(pk-pk)
V
V
mV
(pk-pk)
V
2.4 V
—
600
1.475
V
mV
(pk-pk)
mV
TBD
V
800 mV
(pk-pk)
Preliminary Rev. 0.41
5
5 Page 
Si5110
Functional Description
The Si5110 transceiver is a low power, fully integrated
serializer/deserializer that provides significant margin to
all SONET/SDH jitter specifications. The device
operates from 2.5–2.7 Gbps making it suitable for OC-
48/STM-16, and OC-48/STM-16 applications that use
15/14 forward error correction (FEC) coding. The low
speed receive/transmit interface uses a low power
parallel LVDS interface.
Receiver
The receiver within the Si5110 includes a precision
limiting amplifier, jitter tolerant clock and data recovery
unit (CDR), and 1:4 demultiplexer. In addition,
programmable data slicing and sampling phase
adjustment are provided to support bit-error-rate (BER)
optimization for long haul applications.
Limiting Amplifier
The Si5110 incorporates a high sensitivity limiting
amplifier with sufficient gain to directly accept the output
of transimpedance amplifiers. High sensitivity is
achieved by using a digital calibration algorithm to
cancel out amplifier offsets. This algorithm achieves
superior offset cancellation by using statistical
averaging to remove noise that may degrade more
traditional calibration routines.
The limiting amplifier provides sufficient gain to fully
saturate with input signals that are less than 10 mV
peak-to-peak differential. In addition, input signals that
exceed 1 V peak-to-peak differential will not cause any
performance degradation.
Loss-of-Signal (LOS) Detection
The limiting amplifier includes circuitry that generates a
loss-of-signal (LOS) alarm when the input signal
amplitude on RXDIN falls below an externally controlled
threshold. The Si5110 can be configured to drive the
LOS output low when the differential input amplitude
drops below a threshold set between ~8 mV and 50 mV
pk-pk differential. Approximately 3 dB of hysteresis
prevents unnecessary switching on LOS.
The LOS threshold is set by applying a voltage between
0.20 V and 0.80 V to the LOSLVL input. The voltage
present on LOSLVL maps to an input signal threshold
as follows:
VLOS
=
(---V----L---O----S---L----V---L----–-----0---.--4---x----V----R-----E----F----)-
15
+
30
mV
VLOS is the differential pk-pk LOS threshold referred to
the RXDIN input, VLOSLVL is the voltage applied to the
LOSLVL pin, and VREF is reference voltage output on
the VREF pin.
The LOS detection circuitry is disabled by tieing the
LOSLVL input to the supply (VDD). This forces the LOS
output high.
Slicing Level Adjustment
To support applications that require BER optimization,
the limiting amplifier provides circuitry that supports
adjustment of the 0/1 decision threshold (slicing level)
over a range of ±20 mV when referred to the internally
biased RXDIN input. The slicing level is set by applying
a voltage between 0.20 V and 0.80 V to the SLICELVL
input. The voltage present on SLICELVL sets the slicing
level as follows:
VLEVEL
=
(---V----S---L----I-C----E----–-----0---.--4----x---V----R-----E----F-----)
15
VLEVEL is the slicing level referred to the RXDIN input,
VSLICE is the voltage applied to the SLICE_LVL pin, and
VREF is reference voltage output on the VREF pin.
The slicing level adjustment may be disabled by tieing
the SLCLVL input to the supply (VDD). When slicing is
disabled, the slicing offset is set to 0.0 V relative to
internally biased input common mode voltage for
RXDIN.
Clock and Data Recovery (CDR)
The Si5110 uses an integrated CDR to recover clock
and data from a non-return to zero (NRZ) signal input on
RXDIN. The recovered data clock is used to regenerate
the incoming data by sampling the output of the limiting
amplifier at the center of the NRZ bit period. The
recovered clock and data is then deserialized by a 1:4
demultiplexer and output via a LVDS compatible low
speed interface (RXDOUT[3:0], RXCLK1, and
RXCLK2).
Sample Phase Adjustment
In applications where it is not desirable to recover data
by sampling in the center of the data eye, the Si5110
supports adjustment of the CDR sampling phase across
the NRZ data period. When sample phase adjustment is
enabled, the sampling instant used for data recovery
can be moved over a range of ±22.5° relative to the
center of the incoming NRZ bit period. Adjustment of the
sampling phase is desirable when data eye distortions
are introduced by the transmission medium.
The sample phase is set by applying a voltage between
0.20 V and 0.80 V to the PHASEADJ input. The voltage
present on PHASEADJ maps to sample phase offset as
follows:
Preliminary Rev. 0.41
11
11 Page | ||
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| PDF Descargar | [ Datasheet Si5110-BC.PDF ] | |
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