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Número de pieza | 74ACT174PC | |
Descripción | Hex D-Type Flip-Flop with Master Reset | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 74ACT174PC (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
No Preview Available ! November 1988
Revised November 1999
74AC174 • 74ACT174
Hex D-Type Flip-Flop with Master Reset
General Description
The AC/ACT174 is a high-speed hex D-type flip-flop. The
device is used primarily as a 6-bit edge-triggered storage
register. The information on the D inputs is transferred to
storage during the LOW-to-HIGH clock transition. The
device has a Master Reset to simultaneously clear all flip-
flops.
Features
s ICC reduced by 50%
s Outputs source/sink 24 mA
s ACT174 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC174SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC174SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC174PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT174SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74ACT174SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT174MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT174PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix lettwerw“wX.D” taotatShheeoertd4Uer.cinogmcode.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D5
CP
MR
Q0–Q5
Description
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009935
www.fairchildsemi.com
1 page AC Operating Requirements for AC
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW MR Pulse Width, LOW
tW CP Pulse Width
tREC
Recovery Time
MR to CP
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
AC Electrical Characteristics for ACT
TA = +25°C
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Typ Guaranteed Minimum
2.5 6.5
7.0
2.0 5.0
5.5
1.0 3.0
3.0
0.5 3.0
3.0
1.0 5.5
1.0 5.0
1.0 5.5
1.0 5.0
0 2.5
0 2.0
7.0
5.0
7.0
5.0
2.5
2.0
Units
ns
ns
ns
ns
ns
Symbol
Parameter
fMAX
Maximum Clock
Frequency
tPLH Propagation Delay
CP to Qn
tPHL Propagation Delay
CP to Qn
tPHL Propagation Delay
MR to Qn
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 9)
5.0
5.0
5.0
5.0
Min
165
1.5
1.5
1.5
AC Operating Requirements for ACT
TA = +25°C
CL = 50 pF
Typ
200
7.0
7.0
6.5
Max
10.5
10.5
9.5
TA = −40°C to +85°C
CL = 50 pF
Min Max
140
Units
MHz
1.5 11.5 ns
1.5 11.5 ns
1.5 11.0 ns
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW MR Pulse Width, LOW
tW CP Pulse Width, HIGH or LOW
trec Recovery Time
MR to CP
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
VCC
(V)
(Note 10)
5.0
5.0
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Typ
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
0.5 1.5
1.5
1.0
1.5
1.5
−1.0
2.0
3.0
3.0
0.5
2.0
3.5
3.5
0.5
Units
ns
ns
ns
ns
ns
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
85.0
Units
pF
pF
VCC = OPEN
VCC = 5.0V
Conditions
5 www.fairchildsemi.com
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet 74ACT174PC.PDF ] |
Número de pieza | Descripción | Fabricantes |
74ACT174PC | Hex D-Type Flip-Flop with Master Reset | Fairchild Semiconductor |
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