PDF AV9173-15CS08 Data sheet ( Hoja de datos )

Número de pieza	AV9173-15CS08
Descripción	Video Genlock PLL
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. AV9173 -15 Video Genlock PLL General Description The AV9173-15 provides the analog circuit blocks required for implementing a video genlock dot (pixel) clock generator. It contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). By grouping these critical analog blocks into one IC and utilizing external digital functions, performance and design flexibility are optimized as are development time and system cost. When used with an external clock divider, the AV9173-15 forms a Phase-Locked Loop configured as a frequency synthesizer. The AV9173-15 is designed to accept video horizontal synchronization (h-sync) pulses and produce a video dot clock. A separated, negative-going sync input reference pulse is required at pin 2 (I N). The AV9173-15 is also suited for other clock recovery applications in such areas as data communications. Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1MHz (see specification of output clock range) • Output clock range 0.625 to 37.5 MHz for CLK1, depending on input conditions (see Table 1) on page 2. • Provides h-sync capability with CLK1 outputs 15 to 37.5 MHz for 15kHz input • On-chip loop filter • Single 5 volt power supply • Low power CMOS technology • Small 8-pin DIP or SOIC package Block Diagram AV9173-15RevC051397P ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 1 page AV9173 -15 Electrical Characteristics VDD = +5V ±5%, TA = 0°C to 70°C, unless otherwise stated AC CHARACTERISTICS PARAMETER SYMBOL TEST CONDITIONS Input Clock Rise Time1 Input Clock Fall Time1 Output Rise Time1 ICLKr ICLKf tr1 15pF load; 0.8 to 2.0V Rise time1 Output Fall time1 tr2 15pF load; 20% to 80% VDD tf1 15pF load; 2.0 to 0.8V Fall time1 Output Duty Cycle1 Jitter,1 1 sigma Jitter,1 1 sigma Jitter,1 1 absolute Jitter,1 1 absolute Line-to-line jitter,1 absolute2 Input Frequency,1 IN or FBIN tf2 dt T1s1 T1s2 Tabs 1 Tabs 2 TLabs fi1 15pF load; 80% to 20% VDD 15pF load, VTH =1.4V CLK1 freq.≥ 12.5 MHz CLK1 freq.≥12.5 MHz CLK1 freq.< 12.5 MHz CLK1 freq.< 12.5 MHz fVCO 10 to 75 MHz 12 ≤ fi ≤ 14 kHz CLK1 Frequency3 fCLK1 14 < fi ≤ 17 kHz 17 < fi ≤ 30 kHz 30 < fi ≤ 35 kHz 35 < fi ≤ 1000 kHz MIN — — — — — — 40 — — -400 — — 12.0 22.0 15.0 12.5 7.5 5.0 TYP — — 0.6 1.3 0.6 0.7 47 120 — ±250 — ±4 — — — — — — MAX 10 10 1.5 3.0 1.5 2.0 55 250 1 400 2 — 1000 37.5 37.5 37.5 37.5 37.5 UNITS ns ns ns ns ns ns % ps % ps % ns kHz MHz MHz MHz MHz MHz Notes: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. 2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels. 3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4. 5 5 Page

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