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PDF DS90LV048A Data sheet ( Hoja de datos )
| Número de pieza | DS90LV048A | |
| Descripción | 3V LVDS Quad CMOS Differential Line Receiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 1999
DS90LV048A
3V LVDS Quad CMOS Differential Line Receiver
General Description
The DS90LV048A is a quad CMOS flow-through differential
line receiver designed for applications requiring ultra low
power dissipation and high data rates. The device is de-
signed to support data rates in excess of 400 Mbps (200
MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The DS90LV048A accepts low voltage (350 mV typical) dif-
ferential input signals and translates them to 3V CMOS out-
put levels. The receiver supports a TRI-STATE® function that
may be used to multiplex outputs. The receiver also supports
open, shorted and terminated (100Ω) input fail-safe. The re-
ceiver output will be HIGH for all fail-safe conditions. The
DS90LV048A has a flow-through pinout for easy PCB layout.
The EN and EN* inputs are ANDed together and control the
TRI-STATE outputs. The enables are common to all four re-
ceivers. The DS90LV048A and companion LVDS line driver
(eg. DS90LV047A) provide a new alternative to high power
PECL/ECL devices for high speed point-to-point interface
applications.
Features
n >400 Mbps (200 MHz) switching rates
n Flow-through pinout simplifies PCB layout
n 150 ps channel-to-channel skew (typical)
n 100 ps differential skew (typical)
n 2.7 ns maximum propagation delay
n 3.3V power supply design
n High impedance LVDS inputs on power down
n Low Power design (40mW 3.3V static)
n Interoperable with existing 5V LVDS drivers
n Accepts small swing (350 mV typical) differential signal
levels
n Supports open, short and terminated input fail-safe
n Conforms to ANSI/TIA/EIA-644 Standard
n Industrial temperature operating range (-40˚C to +85˚C)
n Available in SOIC and TSSOP package
Connection Diagram
Dual-in-Line
Functional Diagram
DS100888-1
Order Number DS90LV048ATM, DS90LV048ATMTC
See NS Package Number M16A, MTC16
DS100888-2
ENABLES
EN EN*
H L or Open
All other combinations of ENABLE inputs
INPUTS
RIN+ − RIN−
VID ≥ 0.1V
VID ≤ −0.1V
Full Fail-safe
OPEN/SHORT
or Terminated
X
OUTPUT
ROUT
H
L
H
Z
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100888
www.national.com
1 page  
Applications Information (Continued)
The DS90LV048A differential line receiver is capable of de-
tecting signals as low as 100mV, over a ±1V common-mode
range centered around +1.2V. This is related to the driver off-
set voltage which is typically +1.2V. The driven signal is cen-
tered around this voltage and may shift ±1V around this cen-
ter point. The ±1V shifting may be the result of a ground
potential difference between the driver’s ground reference
and the receiver’s ground reference, the common-mode ef-
fects of coupled noise, or a combination of the two. The AC
parameters of both receiver input pins are optimized for a
recommended operating input voltage range of 0V to +2.4V
(measured from each pin to ground). The device will operate
for receiver input voltages up to VCC, but exceeding VCC will
turn on the ESD protection circuitry which will clamp the bus
voltages.
The DS90LV048A has a flow-through pinout that allows for
easy PCB layout. The LVDS signals on one side of the de-
vice easily allows for matching electrical lengths of the differ-
ential pair trace lines between the driver and the receiver as
well as allowing the trace lines to be close together to couple
noise as common-mode. Noise isolation is achieved with the
LVDS signals on one side of the device and the TTL signals
on the other side.
Power Decoupling Recommendations:
Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1µF
and 0.001µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.
PC Board considerations:
Use at least 4 PCB layers (top to bottom); LVDS signals,
ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
may couple onto the LVDS lines. It is best to put TTL and
LVDS signals on different layers which are isolated by a
power/ground plane(s)
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
Differential Traces:
Use controlled impedance traces which match the differen-
tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be < 10mm long). This will help eliminate re-
flections and ensure noise is coupled as common-mode. In
fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
traces. In addition, noise induced on the differential lines is
much more likely to appear as common-mode which is re-
jected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase differ-
ence between signals which destroys the magnetic field can-
cellation benefits of differential signals and EMI will result.
(Note the velocity of propagation, v = c/Er where c (the
speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely
solely on the autoroute function for differential traces. Care-
fully review dimensions to match differential impedance and
provide isolation for the differential lines. Minimize the num-
ber or vias and other discontinuities on the line.
Avoid 90˚ turns (these cause impedance discontinuities).
Use arcs or 45˚ bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
Termination:
Use a termination resistor which best matches the differen-
tial impedance or your transmission line. The resistor should
be between 90Ω and 130Ω. Remember that the current
mode outputs need the termination resistor to generate the
differential voltage. LVDS will not work without resistor termi-
nation. Typically, connecting a single resistor across the pair
at the receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be < 10mm
(12mm MAX)
Probing LVDS Transmission Lines:
Always use high impedance (> 100kΩ), low
capacitance (< 2 pF) scope probes with a wide bandwidth (1
GHz) scope. Improper probing will give deceiving results.
Cables and Connectors, General Comments:
When choosing cable and connectors for LVDS it is impor-
tant to remember:
Use controlled impedance media. The cables and connec-
tors you use should have a matched differential impedance
of about 100Ω. They should not introduce major impedance
discontinuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax.) for noise re-
duction and signal quality. Balanced cables tend to generate
less EMI due to field canceling effects and also tend to pick
up electromagnetic radiation a common-mode (not differen-
tial mode) noise which is rejected by the receiver.
For cable distances < 0.5M, most cables can be made to
work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (cat-
egory 3) twisted pair cable works well, is readily available
and relatively inexpensive.
Fail-Safe Feature:
The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re-
ceiver, care should be taken to prevent noise from appearing
as a valid signal.
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.
1. Open Input Pins. The DS90LV048A is a quad receiver
device, and if an application requires only 1, 2 or 3 re-
ceivers, the unused channel(s) inputs should be left
OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high
value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.
5 www.national.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead (0.100" Wide) Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90LV048ATMTC
NS Package Number MTC16
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: [email protected]
www.national.com
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Europe
Fax: +49 (0) 1 80-530 85 86
Email: [email protected]
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English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
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Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet DS90LV048A.PDF ] | |
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