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Número de pieza DS90LV031BTM
Descripción 3V LVDS Quad CMOS Differential Line Driver
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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January 2000
DS90LV031B
3V LVDS Quad CMOS Differential Line Driver
General Description
The DS90LV031B is a quad CMOS differential line driver de-
signed for applications requiring ultra low power dissipation
and high data rates. The device is designed to support data
rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage
Differential Signaling (LVDS) technology.
The DS90LV031B accepts low voltage TTL/CMOS input lev-
els and translates them to low voltage (350 mV) differential
output signals. In addition the driver supports a TRI-STATE®
function that may be used to disable the output stage, dis-
abling the load current, and thus dropping the device to an
ultra low idle power state of 13 mW typical. The
DS90LV031B is enhanced over the DS90LV031A in that the
inputs are further ruggedized for excessive undershoot.
The EN and EN* inputs allow active Low or active High con-
trol of the TRI-STATE outputs. The enables are common to
all four drivers. The DS90LV031B and companion line re-
ceiver (DS90LV032A) provide a new alternative to high
power pseudo-ECL devices for high speed point-to-point in-
terface applications.
Features
n >400 Mbps (200 MHz) switching rates
n 0.1 ns typical differential skew
n 0.4 ns maximum differential skew
n 2.0 ns maximum propagation delay
n Ruggedized inputs that can withstand excessive
undershoot
n 3.3V power supply design
n ±350 mV differential signaling
n Low power dissipation (13mW at 3.3V static)
n Interoperable with existing 5V LVDS devices
n Compatible with IEEE 1596.3 SCI LVDS standard
n Compatible with TIA/EIA-644 LVDS standard
n Industrial temperature operating range
n Available in SOIC and TSSOP surface mount packaging
Connection Diagram
Dual-In-Line
Functional Diagram
DS101311-1
Order Number DS90LV031BTM
or DS90LV031BTMTC
See NS Package Number M16A or MTC16
Truth Table
DRIVER
Enables
EN EN*
LH
All other combinations of
ENABLE inputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101311
Input
DIN
X
L
Outputs
DOUT+
Z
DOUT−
Z
LH
HH L
DS101311-2
www.national.com

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DS90LV031BTM pdf
Parameter Measurement Information (Continued)
Typical Application
FIGURE 5. Driver TRI-STATE Delay Waveform
DS101311-7
DS101311-8
FIGURE 6. Point-to-Point Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 6. This configuration provides a clean signaling en-
vironment for the quick edge rates of the drivers. The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically, the characteristic dif-
ferential impedance of the media is in the range of 100. A
termination resistor of 100should be selected to match the
media, and is located as close to the receiver input pins as
possible. The termination resistor converts the current
sourced by the driver into a voltage that is detected by the re-
ceiver. Other configurations are possible such as a
multi-receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance disconti-
nuities as well as ground shifting, noise margin limits, and to-
tal termination loading must be taken into account.
The DS90LV031B differential line driver is a balanced cur-
rent source design. A current mode driver, generally speak-
ing has a high output impedance and supplies a constant
current for a range of loads (a voltage mode driver on the
other hand supplies a constant voltage for a range of loads).
Current is switched through the load in one direction to pro-
duce a logic state and in the other direction to produce the
other logic state. The output current is typically 3.5 mA, a
minimum of 2.5 mA, and a maximum of 4.5 mA. The current
mode requires (as discussed above) that a resistive termi-
nation be employed to terminate the signal and to complete
the loop as shown in Figure 6. AC or unterminated configu-
rations are not allowed. The 3.5 mA loop current will develop
a differential voltage of 350 mV across the 100termination
resistor which the receiver detects with a 250 mV minimum
differential noise margin neglecting resistive line losses
(driven signal minus receiver threshold (350 mV – 100 mV =
250 mV)). The signal is centered around +1.2V (Driver Off-
set, VOS) with respect to ground as shown in Figure 7. Note
that the steady-state voltage (VSS) peak-to-peak swing is
twice the differential voltage (VOD) and is typically 700 mV.
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quies-
cent current remains relatively flat versus switching fre-
quency. Whereas the RS-422 voltage mode driver increases
exponentially in most case between 20 MHz–50 MHz. This
is due to the overlap current that flows between the rails of
the device when the internal gates switch. Whereas the cur-
rent mode driver switches a fixed current between its output
without any substantial overlap current. This is similar to
some ECL and PECL devices, but without the heavy static
ICC requirements of the ECL/PECL designs. LVDS requires
about 80% less current than similar PECL devices. AC speci-
fications for the driver are a tenfold improvement over other
existing RS-422 drivers.
5 www.national.com

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