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Número de pieza | CXL5502M | |
Descripción | CMOS-CCD 1H Delay Line for NTSC | |
Fabricantes | Sony Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CXL5502M (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
No Preview Available ! CXL5502M/N/P
CMOS-CCD 1H Delay Line for NTSC
For the availability of this product, please contact the sales office.
Description
The CXL5502M/N/P are CMOS-CCD delay line ICs
CXL5502M
CXL5502N
that provide 1H delay time for NTSC signals including
14 pin SOP (Plastic) 16 pin SSOP (Plastic)
the external low-pass filter.
The ICs contain a PLL circuit (quadruple progression).
Features
• Single power supply (5V)
• Low power consumption 95mW (Typ.)
• Built-in peripheral circuits
• Clamp level of I/O signal can be selected
• Built-in quadruple PLL circuit
CXL5502P
14 pin DIP (Plastic)
Functions
• 905-bit CCD register
• Clock driver
• Autobias circuit
• Input clamp circuit
• Sample and hold circuit
• PLL circuit (quadruple progression)
Structure
CMOS-CCD
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD
CXL5502M 400 mW
CXL5502N 260 mW
CXL5502P 800 mW
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5% V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0 Vp-p
(0.5Vp-p typ.)
• Clock frequency
fCLK 3.579545 MHz
• Input clock waveform Sine wave
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E89930E79-PS
1 page CXL5502M/N/P
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p, Sine wave)
See "Electrical Characteristics Test Circuit"
Item
Supply
current
Low
frequency
gain
Frequency
response
Differential
gain
Differential
phase
S/H pulse
coupling
S/N ratio
Symbol
Test condition
SW condition Bias condition
Vbias1 (V) Min.
1 2 3 4 5 6 7 (Note 1)
IDDPN
IDDNP
—
—c b b b a—
—
10
aa
GLPN
GLNP
fPN
fNP
DGPN
DGNP
200kHz,
500mVp-p,
sine wave
bb
aab
ab
aa
200kHz ←→ 3.57MHz, b
bb
150mVp-p,
aa bb
sine wave
c aa
5-staircase wave
a bb
(See Note 5)
db
ac
b aa
—
2.1
—
–2
–2
0
DPPN 5-staircase wave
a bb
DPNP (See Note 5)
db
ac
b aa
—
0
CPPN
No signal input
CPNP
bb
VINPN + 0.5
—c a
ba
—
aa
VINNP
SNPN 50% white
video signal
SNNP (See Note 7)
a bb
eb
ad
b aa
—
52
Typ. Max. Unit Note
19 28 mA 2
0 2 dB 3
–1 0 dB 4
5 7%5
5 7 degree 5
— 350 mVp-p 6
56 — dB 7
Notes
(1) VINPN and VINNP are defined as follows.
VINPN and VINNP are the input signal clamp levels of PN and NP modes clamping the video signal sync
tip level.
CXL5502
1
Input
(IN)
VINPN
VINNP
Testing of VINPN and VINNP is executed with a voltmeter under the following SW conditions.
Item
VINPN
VINNP
1
—
—
2
c
c
SW condition
345
bbb
baa
Test
6 7 point
a—
a—
V1
–5–
5 Page Frequency response vs. Supply voltage
0
–1
–2
–3
4.75
5
Supply voltage [V]
5.25
CXL5502M/N/P
Differential gain vs. Supply voltage
10
8
6
4
2
0
4.75
5
Supply voltage [V]
5.25
Frequency response
2
0
–2
–4
–6
10k 100k 1M 10M
Frequency [Hz]
– 11 –
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet CXL5502M.PDF ] |
Número de pieza | Descripción | Fabricantes |
CXL5502M | CMOS-CCD 1H Delay Line for NTSC | Sony Corporation |
CXL5502N | CMOS-CCD 1H Delay Line for NTSC | Sony Corporation |
CXL5502P | CMOS-CCD 1H Delay Line for NTSC | Sony Corporation |
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