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PDF CXA3562R Data sheet ( Hoja de datos )
| Número de pieza | CXA3562R | |
| Descripción | LCD Driver | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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LCD Driver
Description
The CXA3562R is a driver IC developed for use
with Sony polycrystalline silicon TFT LCD panels. It
supports digital 2-parallel and single input, and the
input data is analog demultiplexed into 12 phases and
output. The CXA3562R can directly drive an LCD
panel, and the VCOM setting circuit and precharge
pulse waveform generator are also on-chip.
Features
• Supports 10-bit 2-parallel and single input
• Supports signals up to UXGA
(1/2 clock when using UXGA signals)
• Low output deviation by on-chip output offset cancel circuit
• Supports both line inversion and dot and line inversion
• On-chip timing generator with ECL
• VCOM voltage generation circuit
• Precharge pulse waveform generation circuit
Applications
LCD projectors and other video equipment
Absolute Maximum Ratings (VSS = 0V)
• Supply voltage
VCC 16 V
VDD 5.5 V
• Operating temperature
Topr –20 to +70 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation PD
2300 mW
Recommended Operating Conditions
• Supply voltage
VCC 15.0 to 15.5
VDD 4.75 to 5.25
• Operating temperature
Topr –20 to +70
V
V
°C
CXA3562R
100 pin LQFP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01115-PS
1 page  
CXA3562R
Pin
No.
Symbol
I/O
Standard
voltage level
56
57
SID_OUTX
SID_OUT
O
1.5 to 13.5V
Equivalent circuit
VCC
100k
0.2p
GND
100k
0.2p
145
56
57
Description
Precharge waveform output.
SID_OUTX outputs the inverse
of SID_OUT based on the
output center voltage. These
pins cannot directly drive the
LCD panel, so input to the LCD
panel with an external a buffer.
VDD
58 PRG_LV
59 SID_LV
I 1.0 to 5.0V
58
59
GND
VCC
29µ Precharge level setting.
Adjusts the SID_OUT and
SID_OUTX output potential.
50k PRG_LV is reflected when the
50k PRG input pin (Pin 60) is high,
and SID_LV is reflected when
PRG is low.
60 PRG
I
High: ≥2.0V
Low: ≤0.8V
VDD
60
GND
100k
10k
VCC
50µ
VDD
70µ 10µ
68 VREF_I
I
3.2V
68
GND
VDD
1k
280µ
33.3k
2k
69 VREF_O O
3.2V
20µ
GND
20k
12.4k
69
70 F/H_CNT
High: ≥2.0V
I Low: ≤0.8V
Open: Low
VDD
70
50k
192
200k
GND
–5–
Timing pulse input for switching
the Pins 56 and 57 output levels.
(See PRG_LV (Pin 58) and
SID_LV (Pin 59).)
Internal D/A converter reference
voltage input.
Normally connect directly to
VREF_O.
Reference voltage output.
Normally connect directly to
VREF_I, and connect to GND
through a 0.5 to 1.0µF capacitor.
SH_OUT output timing selection.
High: SH_OUT1 to SH_OUT6
and SH_OUT7 to SH_OUT12
are output at different timing.
Low: SH_OUT1 to SH_OUT12
are output at the same timing.
5 Page 
CXA3562R
Description of Operation
The flow of internal operations is described below.
The digital signals input to D_A9 to D_A0 and D_B9 to D_B0 are internally D/A converted into approximately
1.5V (at VREF_I: 3.2V) analog signals. After that, the signal that has been demultiplexed into 12 phases is
amplified by a factor of three times, inverted at the signal center potential according to FRP, and output.
The output level relative to the digital input changes according to the following settings.
A: SIG_OFST voltage
B: VREF_I voltage
C: SIG.C voltage
VCC
B
1023
512
0
Digital IN
A
Signal Center
A
C
B
SH_OUT
GND
1. Digital input block
The CXA3562R can be set to single input from only the A port or parallel input from both the A and B ports,
and port switching by right/left inversion is also possible in parallel input mode. This makes it possible to
support various systems.
In single input mode, the signal is internally demultiplexed to 2-parallel format and input to the D/A converter.
2. D/A converter block
The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input
from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a
maximum 1.5Vp-p with respect to input data of 000h to 3FFh.
3. Sample-and-hold (S/H) block
The odd-numbered and even-numbered D/A converter outputs are input to the odd-numbered and even-
numbered sample-and-hold blocks, respectively. The signals are converted from time series signals into 6-phase
cyclic parallel signals by the sample-and-hold group which is appropriately controlled by the internal timing
generator. For forward scan, the signals are output in the ascending order of SH_OUT1, SH_OUT2, SH_OUT3
... SH_OUT12. For reverse scan, this order is inverted and the signals are output in descending order. Connect
the signals to the LCD panel according to the order used. The timing of each sample-and-hold pulse is shown
on the following pages. These pulses are not output and are used only inside the IC.
– 11 –
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet CXA3562R.PDF ] | |
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