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PDF CY7B9911V Data sheet ( Hoja de datos )
| Número de pieza | CY7B9911V | |
| Descripción | High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB | |
| Fabricantes | Cypress Semiconductor | |
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CY7B9911V
3.3V RoboClock+
High-Speed Low-Voltage Programmable Skew Clock Buffer
(LV-PSCB)
Features
• All output pair skew <100 ps typical (250 max.)
• 3.75- to 110-MHz output operation
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at 1⁄2 and 1⁄4 input frequency
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
• Zero input-to-output delay
• 50% duty-cycle outputs
• LVTTL outputs drive 50Ω terminated lines
• Operates from a single 3.3V supply
• Low operating current
• 32-pin PLCC package
• Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Functional Description
The CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage
Programmable Skew Clock Buffer (LVPSCB) offers user-
selectable control over system clock functions. These multiple-
output clock drivers provide the system integrator with func-
tions necessary to optimize the timing of high-performance
computer systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive terminated
transmission lines with impedances as low as 50Ω while deliv-
ering minimal and specified output skews and full-swing logic levels
(LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission
line delay effects to be canceled. When this “zero delay” capa-
bility of the LVPSCB is combined with the selectable output
skew functions, the user can create output-to-output delays of
up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
Logic Block Diagram
Pin Configuration
TEST
FB
REF
PHASE
FREQ FILTER
DET
FS
VCO AND
TIME UNIT
GENERATOR
4F0
4F1
SELECT
INPUTS
(THREE
LEVEL)
3F0
3F1
2F0
2F1
SKEW
SELECT
MATRIX
PLCC
4 3 2 1 32 31 30
3F1 5
29 2F0
4Q0 4F0 6
28 GND
4F1 7
27 1F1
4Q1
VCCQ 8
26 1F0
3Q0
VCCN 9
CY7B9911V
25 VCCN
4Q1 10
3Q1
4Q0 11
24 1Q0
23 1Q1
2Q0 GND 12
22 GND
GND 13
21 GND
2Q1 14 15 16 17 18 19 20
1F0 1Q0
1F1
1Q1
7B9911V–1
7B9911V–2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1, 1999
1 page  
CY7B9911V
3.3V RoboClock+
AC Test Loads and Waveforms
VCC
R1 R1=100
R2=100
CL = 30 pF
CL R2 (Includes fixture and probe capacitance)
TTL AC Test Load
7B9911V–4
3.0V
2.0V
Vth =1.5V
0.8V
0.0V
≤1ns
TTL Input Test Waveform
2.0V
Vth =1.5V
0.8V
≤1ns
7B9911V–5
Switching Characteristics Over the Operating Range[2, 11]
CY7B9911V–5
Parameter
fNOM
Operating Clock
Frequency in MHz
Description
FS = LOW[1, 2]
FS = MID[1, 2]
FS = HIGH[1, 2 , 3]
Min.
15
25
40
Typ.
Max.
30
50
110
Unit
MHz
tRPWH
tRPWL
tU
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
tPD
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew (XQ0, XQ1)[13, 14]
Zero Output Skew (All Outputs)[13, 15]
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[13, 17]
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[13, 17]
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[13, 17]
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[13, 17]
Device-to-Device Skew[12, 18]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[19]
Output HIGH Time Deviation from 50%[20]
Output LOW Time Deviation from 50%[20]
Output Rise Time[20, 21]
Output Fall Time[20, 21]
PLL Lock Time[22]
Cycle-to-Cycle Output
Jitter
RMS[12]
Peak-to-Peak[12]
5.0
5.0
– 0.5
– 1.0
0.15
0.15
See Table 1
0.1 0.25
0.25 0.5
0.6 0.7
0.5 1.0
0.5 0.7
0.5 1.0
1.25
0.0 +0.5
0.0 +1.0
2.5
3
1.0 1.5
1.0 1.5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
Notes:
11. Test measurement levels for the CY7B9911V are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown
in the AC Test Loads and Waveforms unless otherwise specified.
12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with 30 pF and terminated with 50Ω to VCC/2 (CY7B9911V).
14. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
15. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
16. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
17. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-
2 or Divide-by-4 mode).
18. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.)
19. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
20. Specified with outputs loaded with 30 pF for the CY7B9911V–5 and –7 devices. Devices are terminated through 50Ω to VCC/2.tPWH is measured at 2.0V. tPWL is
measured at 0.8V.
21. tORISE and tOFALL measured between 0.8V and 2.0V.
22. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
5
5 Page 
CY7B9911V
3.3V RoboClock+
Ordering Information
Accuracy
(ps)
Ordering Code
500 CY7B9911V–5JC
700 CY7B9911V–7JC
Document #: 38-00765-B
Package Diagram
Package
Name
J65
J65
Package Type
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier J65
Operating
Range
Commercial
Commercial
51-85002-B
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CY7B9911V.PDF ] | |
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