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PDF CY7B923 Data sheet ( Hoja de datos )
| Número de pieza | CY7B923 | |
| Descripción | HOTLink Transmitter/Receiver | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7B923
CY7B933
HOTLink™ Transmitter/Receiver
Features
• Fibre Channel compliant
• IBM ESCON® compliant
• DVB-ASI compliant
• ATM compliant
• 8B/10B-coded or 10-bit unencoded
• Standard HOTLink: 160–330 Mbps
• High Speed HOTLink: 160–400 Mbps for high speed ap-
plications
• Low Speed HOTLink: 150–160 Mbps for Low Cost Fiber
applications
• TTL synchronous I/O
• No external PLL components
• Triple PECL 100K serial outputs
• Dual PECL 100K serial inputs
• Low power: 350 mW (Tx), 650 mW (Rx)
• Compatible with fiber-optic modules, coaxial cable, and
twisted pair media
• Built-In Self-Test
• Single +5V supply
• 28-pin SOIC/PLCC/LCC
• 0.8µ BiCMOS
Functional Description
The CY7B923 HOTLink™ Transmitter and CY7B933 HOTLink
Receiver are point-to-point communications building blocks
that transfer data over high-speed serial links (fiber, coax, and
twisted pair). Standard HOTLink data rates range from
160-330 Mbits/second. Higher speed HOTLink is also avail-
able for high speed applications (160-400 Mbits/second), as
well as for those Low Cost applications HOTLink-155 (150-160
Mbits/second operations). Figure 1 illustrates typical connec-
tions to host systems or controllers.
Eight bits of user data or protocol information are loaded into
the HOTLink transmitter and are encoded. Serial data is shift-
ed out of the three differential positive ECL (PECL) serial ports
at the bit rate (which is 10 times the byte rate).
The HOTLink receiver accepts the serial bit stream at its dif-
ferential line receiver inputs and, using a completely integrated
PLL Clock Synchronizer, recovers the timing information nec-
essary for data reconstruction. The bit stream is deserialized,
decoded, and checked for transmission errors. Recovered
bytes are presented in parallel to the receiving host along with
a byte-rate clock.
The 8B/10B encoder/decoder can be disabled in systems that
already encode or scramble the transmitted data. I/O signals
are available to create a seamless interface with both asyn-
chronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A Built-In Self-Test pattern generator and checker
allows testing of the transmitter, receiver, and the connecting
link as a part of a system diagnostic check.
HOTLink devices are ideal for a variety of applications where
a parallel interface can be replaced with a high-speed
point-to-point serial link. Applications include interconnecting
workstations, servers, mass storage, and video transmission
equipment.
CY7B923 Transmitter Logic Block Diagram
RP ENN ENA
SC/D (Da)
D0− 7
(Db − h)
SVS(Dj)
FOTO
CKW
ENABLE
INPUT REGISTER
CLOCK
GENERATOR
MODE
BISTEN
TEST
LOGIC
ENCODER
SHIFTER
OUTA
OUTB
OUTC
B923–1
CY7B933 Receiver Logic Block Diagram
RF
A/B
INA+
INA−
INB (INB+)
SI(INB− )
SO
REFCLK
MODE
BISTEN
PECL
TTL
CLOCK
SYNC
TEST
LOGIC
FRAMER
DATA SHIFTER
DECODER
REGISTER
DECODER
OUTPUT
REGISTER
HOTLink is a trademark of cypress Semiconductor Corporation.
ESCON is a registered trademark of IBM.
CKR
RDY
Q0− 7
(Qb − h)
RVS(Qj)
SC/D (Qa) B923–2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
April 5, 1999
1 page  
CY7B923
CY7B933
CY7B933 HOTLink Receiver (continued)
Name
I/O
Description
INB
(INB+)
PECL in
(Diff In)
Serial Data Input B. This pin is either a single-ended PECL data receiver (INB) or half of the INB
differential pair. If SO is wired to VCC, then INB± can be used as differential line receiver interchangeably
with INA±. If SO is normally connected and loaded, INB becomes a single-ended PECL 100K (+5V refer-
enced) serial data input. INB is used as the test clock while in Test mode.
SI
(INB−)
PECL in
(Diff In)
Status Input. This pin is either a single-ended PECL status monitor input (SI) or half of the INB
differential pair. If SO is wired to VCC, then INB± can be used as differential line receiver interchangeably
with INA±. If SO is normally connected and loaded, SI becomes a single-ended PECL 100K (+5V referenced)
status monitor input, which is translated into a TTL-level signal at the SO pin.
SO TTL Out Status Out. SO is the TTL-translated output of SI. It is typically used to translate the Carrier Detect
output from a fiber-optic receiver connected to SI. When this pin is normally connected and loaded
(without any external pull-up resistor), SO will assume the same logical level as SI and INB will
become a single-ended PECL serial data input. If the status monitor translation is not desired, then
SO may be wired to VCC and the INB± pair may be used as a differential serial data input.
RF
TTL In
Reframe Enable. RF controls the Framer logic in the Receiver. When RF is held HIGH, each SYNC
(K28.5) symbol detected in the shifter will frame the data that follows. If is HIGH for 2,048 consecutive
bytes, the internal framer switches to double-byte mode. When RF is held LOW, the reframing logic
is disabled. The incoming data stream is then continuously deserialized and decoded using byte
boundaries set by the internal byte counter. Bit errors in the data stream will not cause alias SYNC
characters to reframe the data erroneously.
REFCLK
MODE
BISTEN
VCCN
VCCQ
GND
TTL In
3-Level In
TTL In
Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL.
REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream.
REFCLK must be connected to a crystal-controlled time base that runs within the frequency limits of
the Tx/Rx pair, and the frequency must be the same as the transmitter CKW frequency (within
CKW±0.1%).
Decoder Mode Select. The level on the MODE pin determines the decoding method to be used.
When wired to GND, MODE selects 8B/10B decoding. When wired to VCC, registered shifter contents
bypass the decoder and are sent to Qa−j directly. When left floating (internal resistors hold the MODE pin at
VCC/2) the internal bit clock generator is disabled and INB becomes the bit rate test clock to be used for factory
test. In typical applications, MODE is wired to VCC or GND.
Built-In Self-Test Enable. When BISTEN is LOW the Receiver awaits a D0.0 (sent once per BIST loop)
character and begins a continuous test sequence that tests the functionality of the Transmitter, the Receiver,
and the link connecting them. In BIST mode the status of the test can be monitored with RDY and RVS
outputs. In normal use BISTEN is held HIGH or wired to VCC. BISTEN has the same timing as Q0−7.
Power for output drivers.
Power for internal circuitry.
Ground.
CY7B923 HOTLink Transmitter Block Diagram
Description
Input Register
The Input register holds the data to be processed by the HOT-
Link transmitter and allows the input timing to be made consis-
tent with standard FIFOs. The Input register is clocked by CKW
and loaded with information on the D0−7, SC/D, and SVS pins.
Two enable inputs (ENA and ENN) allow the user to choose when
data is loaded in the register. Asserting ENA (Enable, active LOW)
causes the inputs to be loaded in the register on the rising edge of
CKW. If ENN (Enable Next, active LOW) is asserted when CKW
rises, the data present on the inputs on the next rising edge of CKW
will be loaded into the Input register. If neither ENA nor ENN are
asserted LOW on the rising edge of CKW, then a SYNC (K28.5)
character is sent. These two inputs allow proper timing and function
for compatibility with either asynchronous FIFOs or clocked FIFOs
without external logic, as shown in Figure 5.
In BIST mode, the Input register becomes the signature pat-
tern generator by logically converting the parallel Input register
into a Linear Feedback Shift Register (LFSR). When enabled,
this LFSR will generate a 511-byte sequence that includes all
Data and Special Character codes, including the explicit viola-
tion symbols. This pattern provides a predictable but pseu-
do-random sequence that can be matched to an identical
LFSR in the Receiver.
Encoder
The Encoder transforms the input data held by the Input reg-
ister into a form more suitable for transmission on a serial in-
terface link. The code used is specified by ANSI X3.230 (Fibre
Channel) and the IBM ESCON channel (code tables are at the
end of this datasheet). The eight D0−7 data inputs are converted
to either a Data symbol or a Special Character, depending upon the
state of the SC/D input. If SC/D is HIGH, the data inputs represent
a control code and are encoded using the Special Character code
5
5 Page 
Switching Waveforms for the CY7B923 HOTLink Transmitter
CKW
tCPWL
tCPWH
tCKW
ENA
D0–D7,
SC/D,
SVS,
BISTEN
RP
tSENP
NOTES 10,11
tSD
tHENP
VALID DATA
tPDF
tSD
tHD
tPDR
tPPWH
DISABLED
ENABLED
CY7B923
CY7B933
B923–11
CKW
ENN
D0–D7,
SC/D,
SVS,
BISTEN
tCPWL
tSD
tCPWH
tCKW
tHD
VALID DATA
tSD tHD
B923–12
11
11 Page | ||
| Páginas | Total 35 Páginas | |
| PDF Descargar | [ Datasheet CY7B923.PDF ] | |
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