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PDF CY7C9335 Data sheet ( Hoja de datos )
| Número de pieza | CY7C9335 | |
| Descripción | SMPTE-259M/DVB-ASI Descrambler/Framer-Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C9335
Features
• Fully compatible with SMPTE-259M
— SMPTE-125M compliant for 4:2:2 component video
— SMPTE-244M compliant for 4fsc composite video
• Fully compatible with DVB-ASI
• Operates from a single +5V or −5V supply
• 100-pin TQFP package
• Decodes 10-bit parallel digital streams for any rate from
16−40 M characters/sec (160−400 Mbits/sec serial)
• Operates with CY7B9334 SMPTE HOTLink™ deserializ-
er/receiver
• X9 + X4 + 1 descrambler and NRZI-to-NRZ decoder may
be bypassed for raw data output
Functional Description
SMPTE-259M Operation
The CY7C9335 is a CMOS integrated circuit designed to de-
code SMPTE-125M and SMPTE-244M bit-parallel digital char-
acters (or other data formats) using the SMPTE-259M decod-
ing rules. Following decoding, the characters are framed by
locating the 30-bit TRS pattern in the parallel character
stream. The framed characters are then output.
SMPTE-259M/DVB-ASI
Descrambler/Framer-Controller
The inputs of the CY7C9335 are designed to be directly mated
to a CY7B9334 HOTLink receiver, which converts the
SMPTE-259M compatible high-speed serial data stream into
10-bit parallel characters.
This device performs both TRS (sync) detection and framing,
data descrambling with the SMPTE-259M X9 + X4 + 1 algo-
rithm, and NRZI-to-NRZ decoding. These functions operate at
any character rate from 16 to 40 MHz. For those systems op-
erating with non-SMPTE-259M compliant video streams (or for
diagnostic purposes), the descrambler and NRZI decoding
functions can be disabled.
DVB-ASI Operation
The CY7C9335 also contains the necessary multiplexers, con-
trol inputs and outputs, to control a DVB-ASI compliant video
stream. DVB-ASI operation is enabled through activation of a
single input signal. This allows a single serial-to-parallel input
port to support both SMPTE and DVB data streams under soft-
ware or hardware control.
In DVB-ASI mode the CY7C9335 automatically enables both
the 8B/10B decoder and multi-byte framer present in the
CY7B9334 receiver/deserializer. All error detection, fill, and
command codes are detected and output by the CY7C9335.
The CY7C9335 operates from a single +5V or −5V supply. It is
available in a 100-pin TQFP space saving package.
Logic Block Diagram
D9(RVS)
D8
D7
D6
D5
D4
D3
D2
D1
D0(SC/D)
19 10
10
11 10
10
4
SYNC_EN
BYPASS
DVB_EN
CKR
OE
HOTLink is a trademark of Cypress Semiconductor Corporation.
RF
A/B
P D 9( S V S )
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0(SC/D)
H_SYNC
SYNC_ERR
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 19, 1999
1 page  
CY7C9335
Electrical Characteristics Over the Operating Range
Parameter
Description
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage
IIX Input Load Current
IOZ Output Leakage Current
IOS Output Short Circuit Current[2, 3]
Test Conditions
IOH = −3.2 mA, VCC = Min.
IOL = 16.0 mA, VCC = Min
Note 1
Note 1
GND ≤ VI ≤ VCC
GND ≤ VO ≤ VCC, Output Disabled
VCC = Max., VOUT = 0.5V
Min.
2.4
2.0
−0.5
−10
−50
−30
Max.
0.5
7.0
0.8
+10
+50
−160
Unit
V
V
V
V
µA
µA
mA
Capacitance[3]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
f = 1 MHz, VCC = 5.0V
Max.
10
12
Unit
pF
pF
AC Test Loads and Waveforms
TTL OUTPUTS
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
238Ω
(a)
238Ω
5V
3.0V
OUTPUT
170Ω
5 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
OUTPUT
170 GND
< 2 ns
(b)
THÉVENIN
99 Ω
EQUIVALENT
2.08V
ALL INPUT PULSES
90%
10%
90%
10%
< 2 ns
7C9335–9
Switching Characteristics Over the Operating Range[4]
CY7C9335-27 CY7C9335-40
Parameter
Description
Min. Max. Min. Max. Unit
tPD Input to Output (DVB_EN to RF only)
20 15 ns
tSD Input Data Set-Up Time to CKR
10 8
ns
tHD Input Data Hold Time to CKR
0 0 ns
tCPRH
CKR Pulse Width HIGH
6.5 6.5
ns
tCPRL
tCKR
CKR Pulse Width LOW
Read Clock Cycle[5]
6.5 6.5
30 62.5 25 62.5
ns
ns
tA Output Access Time from CKR
10 8 ns
tH Output Hold Time from CKR
4 3 ns
tEA Input to Output Enable
tER Input to Output Disable [6]
24 20 ns
24 20 ns
Notes:
1. These are absolute values with respect to device ground. All overshoots with respect to system or tester noise are included.
2. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
3. Tested initially and after any design or process changes that may effect these parameters.
4. All AC parameters are with all outputs switching.
5. The clock period may be extended by up to 90% for a single clock cycle when framing occurs in DVB-ASI mode.
6. Test load (b) used for this parameter. Test load (a) used for all other AC parameters.
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CY7C9335.PDF ] | |
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