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PDF CY7C67200 Data sheet ( Hoja de datos )

Número de pieza CY7C67200
Descripción EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! CY7C67200 Hoja de datos, Descripción, Manual

CY7C67200
EZ-OTG™
Programmable USB On-The-Go
Host/Peripheral Controller
Cypress Semiconductor Corporation
Document #: 38-08014 Rev. *E
• 3901 North First Street
• San Jose, CA 95134 • 408-943-2600
Revised September 16, 2003

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CY7C67200 pdf
CY7C67200
TABLE OF CONTENTS (continued)
14.0 AC TIMING CHARACTERISTICS ................................................................................................ 87
14.1 Reset Timing ........................................................................................................................... 87
14.2 Clock Timing ........................................................................................................................... 88
14.3 I2C EEPROM Timing .............................................................................................................. 88
14.4 HPI (Host Port Interface) Write Cycle Timing ......................................................................... 89
14.5 HPI (Host Port Interface) Read Cycle Timing ......................................................................... 90
14.6 HSS BYTE Mode Transmit ..................................................................................................... 91
14.7 HSS Block Mode Transmit ...................................................................................................... 91
14.8 HSS BYTE and BLOCK Mode Receive .................................................................................. 91
14.9 Hardware CTS/RTS Handshake ............................................................................................. 92
15.0 REGISTER SUMMARY ................................................................................................................ 93
16.0 ORDERING INFORMATION ........................................................................................................ 97
17.0 PACKAGE DIAGRAMS ............................................................................................................... 97
Document #: 38-08014 Rev. *E
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CY7C67200 arduino
CY7C67200
4.0 Interface Descriptions
EZ-OTG has a variety of interface options for connectivity, with several interface options available. See Table 4-1 to understand
how the interfaces share pins and can coexist. Below are some general guidelines:
• I2C EEPROM and OTG do not conflict with any interfaces
• HPI is mutually exclusive to: HSS, SPI, and UART.
Table 4-1. Interface Options for GPIO Pins
GPIO Pins
GPIO31
GPIO30
GPIO29
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
HPI
INT
nRD
nWR
nCS
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HSS
CTS
RTS
RXD
TXD
SPI UART I2C
OTG
SCL/SDA
SCL/SDA
OTGID
MOSI
SCK
nSSI
MISO
TX
RX
4.1 USB Interface
EZ-OTG has two built-in Host/Peripheral SIEs that each have a single USB transceiver, meeting the USB 2.0 specification
requirements for full- and low-speed (high-speed is not supported). In Host mode, EZ-OTG supports two downstream ports, each
support control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-OTG supports one peripheral port with eight
endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints
1 though 7 support Interrupt, Bulk (up to 64 Bytes/packet), or Isochronous transfers (up to 1023 Bytes/packet size). EZ-OTG also
supports a combination of Host and Peripheral ports simultaneously. EZ-OTG also supports a combination of Host and Peripheral
ports simultaneously as shown in Table 4-2.
Document #: 38-08014 Rev. *E
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