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PDF CY7C66013 Data sheet ( Hoja de datos )
| Número de pieza | CY7C66013 | |
| Descripción | Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C66013
CY7C66113
Full-Speed USB (12 Mbps) Peripheral
Controller with Integrated Hub
Cypress Semiconductor Corporation
Document #: 38-08024 Rev. *A
• 3901 North First Street
• San Jose, CA 95134 • 408-943-2600
Revised March 6, 2003
1 page  
CY7C66013
CY7C66113
LIST OF TABLES
Table 4-1. Pin Assignments .................................................................................................................. 11
Table 4-2. I/O Register Summary ......................................................................................................... 11
Table 4-3. Instruction Set Summary ..................................................................................................... 13
Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity .............................................. 21
Table 12-1. HAPI Port Configuration .................................................................................................... 25
Table 12-2. I2C Port Configuration ........................................................................................................ 25
Table 13-1. I2C Status and Control Register Bit Definitions .................................................................. 26
Table 14-1. Port 2 Pin and HAPI Configuration Bit Definitions ............................................................. 27
Table 16-1. Interrupt Vector Assignments ............................................................................................ 31
Table 18-1. Control Bit Definition for Downstream Ports ...................................................................... 36
Table 18-2. Control Bit Definition for Upstream Port ............................................................................ 39
Table 19-1. Memory Allocation for Endpoints ..................................................................................... 40
Table 20-1. USB Register Mode Encoding ........................................................................................... 44
Table 20-2. Decode Table for Table 20-3: “Details of Modes for Differing Traffic Conditions” ............. 45
Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for the decode legend) 46
Document #: 38-08024 Rev. *A
Page 5 of 58
5 Page 
CY7C66013
CY7C66113
4.0 Product Summary Tables
4.1 Pin Assignments
Table 4-1. Pin Assignments
Name
D+[0], D–[0]
D+[1], D–[1]
D+[2], D–[2]
D+[3], D–[3]
D+[4], D–[4]
P0[7:0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1[7:0]
I/O
P2[7:0]
I/O
P3[6:0]
I/O
DAC[7:0]
I/O
XTALIN
XTALOUT
VPP
VCC
GND
VREF
IN
OUT
IN
48-Pin
56-Pin
Description
8, 9 8, 9 Upstream port, USB differential data.
12, 13
13, 14
Downstream port 1, USB differential data.
15, 16
16, 17
Downstream port 2, USB differential data.
40, 41
48, 49
Downstream port 3, USB differential data.
35, 36
44, 45
Downstream port 4, USB differential data.
21, 25, 22, 26, 22, 32, 23, 33, GPIO Port 0.
23, 27, 24, 28 24, 34, 25, 35
6, 43, 5, 44, 4, 6, 51, 5, 52, 4, GPIO Port 1.
45, 47, 46
53, 55, 54
19, 30, 18, 31, 20, 38, 19, 39, GPIO Port 2.
17, 33, 14, 34 18, 41, 15, 42
37, 10, 39, 7, 42 43, 12, 46, 10, GPIO Port 3, capable of sinking 12 mA (typical).
47, 7, 50
n/a 21, 29, 26, 30, Digital to Analog Converter (DAC) Port with programmable current
27, 31, 28, 37 sink outputs. DAC[1:0] offer a programmable range of 3.2 to 16 mA
typical. DAC[7:2] have a programmable sink current range of 0.2 to 1.0
mA typical.
2 2 6-MHz crystal or external clock input.
1 1 6-MHz crystal out.
29 36 Programming voltage supply, tie to ground during normal
operation.
48 56 Voltage supply.
11, 20, 32, 38 11, 40
Ground.
3 3 External 3.3V supply voltage for the differential data output buffers
and the D+ pull-up.
4.2 I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected
port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port. Indexed I/O Write
(IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to
the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X.
All undefined registers are reserved. It is important not to write to reserved registers as this may cause an undefined operation
or increased current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written
with ‘0.’
Table 4-2. I/O Register Summary
Register Name
Port 0 Data
Port 1 Data
Port 2 Data
Port 3 Data
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 2 Interrupt Enable
Port 3 Interrupt Enable
GPIO Configuration
I/O Address Read/Write
Function
0x00 R/W GPIO Port 0 Data
0x01 R/W GPIO Port 1 Data
0x02 R/W GPIO Port 2 Data
0x03 R/W GPIO Port 3 Data
0x04
W
Interrupt Enable for Pins in Port 0
0x05
W
Interrupt Enable for Pins in Port 1
0x06
W
Interrupt Enable for Pins in Port 2
0x07
W
Interrupt Enable for Pins in Port 3
0x08 R/W GPIO Port Configurations
Page
20
20
20
20
21
22
22
22
20
Document #: 38-08024 Rev. *A
Page 11 of 58
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C66013.PDF ] | |
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