PDF CY7C4221V-15JC Data sheet ( Hoja de datos )

Número de pieza	CY7C4221V-15JC
Descripción	Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Fabricantes	Cypress Semiconductor
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Features Functional Description • High-speed, low-power, first-in, first-out (FIFO) memories • 64 x 9 (CY7C4421V) • 256 x 9 (CY7C4201V) • 512 x 9 (CY7C4211V) • 1K x 9 (CY7C4221V) • 2K x 9 (CY7C4231V) • 4K x 9 (CY7C4241V) • 8K x 9 (CY7C4251V) • High-speed 66-MHz operation (15-ns read/write cycle time) • Low power (ICC = 20 mA) • 3.3V operation for low power consumption and easy integration into low-voltage systems • 5V-tolerant inputs VIH max= 5V • Fully asynchronous and simultaneous read and write operation • Empty, Full, and Programmable Almost Empty and Almost Full status flags • TTL compatible • Output Enable (OE) pin • Independent read and write enable pins • Center power and ground pins for reduced noise • Width expansion capability • Space saving 32-pin 7 mm × 7 mm TQFP • 32-pin PLCC The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multi- processor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock (WCLK) and two Write Enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a Free-Running Read Clock (RCLK) and two Read Enable Pins (REN1, REN2). In addition, the CY7C42X1V has an Output Enable Pin (OE). The Read (RCLK) and Write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run indepen- dently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. Logic Block Diagram WCLK WEN1 WEN2/LD WRITE CONTROL WRITE POINTER D0 − 8 INPUT REGISTER Dual Port RAM Array 64 x 9 8Kx 9 Pin Configuration PLCC Top View FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER EF PAE PAF FF D1 D0 PAF PAE GND REN1 RCLK REN2 OE 4 3 2 1 32 3130 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 22 13 21 141516 171819 20 RS WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5 TQFP Top View RS RESET LOGIC THREE-STATE OUTPUTREGISTER Q0 − 8 OE READ CONTROL RCLK REN1 REN2 D1 D0 PAF PAE GND REN1 RCLK REN2 32 31 30 29 28 27 26 25 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5 Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-06010 Rev. A Revised August 22, 2003 1 page Table 2. Status Flags CY7C4421V 0 1 to n[2] (n+1) to 32 33 to (64−(m+1)) (64−m)[3] to 63 64 CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Number of Words in FIFO CY7C4201V 0 1 to n[2] (n+1) to 128 129 to (256−(m+1)) (256−m)[3] to 255 256 CY7C4211V 0 1 to n[2] (n+1) to 256 257 to (512−(m+1)) (512−m)[3] to 511 512 FF PAF PAE EF HH LL HH LH HH HH HH HH HL HH LL HH CY7C4221V 0 1 to n[2] (n+1) to 512 513 to (1024 −(m+1)) (1024−m)[3] to 1023 1024 Number of Words in FIFO CY7C4231V CY7C4241V 0 1 to n[2] 0 1 to n[2] (n+1) to 1024 (n+1) to 2048 1025 to (2048 −(m+1)) 2049 to (4096 −(m+1)) (2048−m)[3] to 2047 (4096−m)[3] to 4095 2048 4096 CY7C4251V 0 1 to n[2] (n+1) to 4096 4097 to (8192 −(m+1)) (8192−m)[3] to 8191 8192 FF PAF PAE HH L HH L HH H HH H HL H LL H EF L H H H H H Width Expansion Configuration Flag Operation Word width may be increased simply by connecting the corre- sponding input control signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demon- strates a 18-bit word width by using two CY7C42X1Vs. Any word width can be attained by adding additional CY7C42X1Vs. When the CY7C42X1V is in a Width Expansion Configuration, the Read Enable (REN2) control input can be grounded (see Figure 2). In this configuration, the Write Enable 2/Load (WEN2/LD) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. Notes: 2. n = Empty Offset (n=7 default value). 3. m = Full Offset (m=7 default value). The CY7C42X1 devices provide four flag pins to indicate the condition of the FIFO contents. Empty, Full, PAE, and PAF are synchronous. Full Flag The Full Flag (FF) will go LOW when device is full. Write opera- tions are inhibited whenever FF is LOW regardless of the state of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN1 and REN2. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK. Document #: 38-06010 Rev. A Page 5 of 17 5 Page CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLK D0 –D8 WEN1 tDS tENS D0 (FIRSTVALID WRITE) [16] tFRL D1 D2 D3 D4 WEN2 (if applicable) RCLK EF REN1, REN2 tSKEW1 tREF tA [17] tA Q0 –Q8 OE tOLZ tOE D0 D1 Notes: 16. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). 17. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06010 Rev. A Page 11 of 17 11 Page

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