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PDF LTC1703 Data sheet ( Hoja de datos )
| Número de pieza | LTC1703 | |
| Descripción | Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC1703 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LTC1703
Dual 550kHz Synchronous
2-Phase Switching Regulator
Controller with 5-Bit VID
FEATURES
s Two Independent PWM Controllers in One Package
s Side 1 Output Is Compliant with Intel Mobile
VID Specifications (Includes 5-Bit DAC)
s 0.9V to 2.0V Output Voltage with 25mV/50mV Steps
s Two Sides Run Out-of-Phase to Minimize CIN
s All N-Channel External MOSFET Architecture
s No External Current Sense Resistor
s Precision Internal 0.8V ±1% Reference
s 550kHz Switching Frequency Minimizes External
Component Size
s Very Fast Transient Response
s Up to 25A Output Current per Channel
s Low Shutdown Current: < 100µA
s Small 28-Pin SSOP Package
U
APPLICATIO S
s Mobile Pentium® III Processor Systems
s Microprocessor Core and I/O Supplies
s Multiple Logic Supply Generator
s High Efficiency Power Conversion
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation. Pentium is a registered trademark
of Intel Corporation.
DESCRIPTIO
The LTC®1703 is a dual switching regulator controller opti-
mized for high efficiency with low input voltages. It includes
two complete, on-chip, independent switching regulator
controllers. Each is designed to drive a pair of external
N-channel MOSFET devices in a voltage mode feedback,
synchronous buck configuration. The LTC1703 includes
digital output voltage adjustment on side 1 that conforms to
the Intel Mobile VID specification. It uses a constant-
frequency, true PWM design switching at 550kHz, minimiz-
ing external component size and cost and optimizing load
transient performance. The synchronous buck architecture
automatically shifts to discontinuous and then to Burst
ModeTM operation as the output load decreases, ensuring
maximum efficiency over a wide range of load currents.
The LTC1703 features an onboard reference trimmed to 1%
and delivers better than 1.5% regulation at the converter
outputs. An optional latching FAULT mode protects the load
if the output rises 15% above the intended voltage. Each
channel can be enabled independently; with both channels
disabled, the LTC1703 shuts down and supply current drops
below 100µA.
TYPICAL APPLICATIO
Dual Output Mobile Pentium III Processor Supply
VOUT1
0.9V
TO 2V
15A
GND
DCP1
MBR0520LT1
L1 QT1
1µH
1µF
DCP2
MBR0520LT1
LTC1703
+ COUT1
180µF
QB1A
QB1B
CCP1
1µF
1
2
PVCC
BOOST1
3 BG1
IMAX2
BOOST2
28
27
BG2 26
4V
×6
4 TG1
5 SW1
TG2 25
SW2 24
RIMAX1,18.7k
6
7
IMAX1
FCB
PGND 23
FAULT 22
8 RUN/SS1 RUN/SS2 21
CSS1
9 COMP1
COMP2 20
0.22µF
R21
100k
C31
220pF
C11
220pF
C21
15pF
R31, 10k
10 SGND
11 FB1
12 SENSE
13 VID0
14 VID1
FB2 19
VCC
VID4
18
17
VID3 16
VID2 15
L1: MURATA LQT12535C1R5N12
L2: COILTRONICS UP2B-2R2
QT1, QB1A, QB1B: INTERNATIONAL RECTIFIER IRF7811
QT2, QB2: 1/2 FAIRCHILD NDS8926
VID0
VID1
VID2
VID3
VID4
QT2
L2
2.2µH
CCP2
1µF
QB2
RIMAX2
20k
+
R22, 100k
C22
15pF
C12
220pF
1µF
+ CIN
150µF
10V
×2
VIN
4.5V TO 5.5V
COUT2
180µF
4V
R12
10.2k
0.1%
C32
2200pF
R32
1k
10Ω
VOUT2
1.5V
3A
RB2
11.5k
0.1%
GND
GND
CSS2
0.22µF
1703 TA01
1
1 page  
LTC1703
PI FU CTIO S
PVCC (Pin 1): Driver Power Supply Input. PVCC provides
power to the two BGn output drivers. PVCC must be
connected to a voltage high enough to fully turn on the
external MOSFETs QB1 and QB2. PVCC should generally
be connected directly to VIN. PVCC requires at least a 1µF
bypass capacitor directly to PGND.
BOOST1 (Pin 2): Controller 1 Top Gate Driver Supply. The
BOOST1 pin supplies power to the floating TG1 driver.
BOOST1 should be bypassed to SW1 with a 1µF capacitor.
An additional Schottky diode from VIN to BOOST1 pin will
create a complete floating charge-pumped supply at
BOOST1. No other external supplies are required.
BG1 (Pin 3): Controller 1 Bottom Gate Drive. The BG1 pin
drives the gate of the bottom N-channel synchronous
switch MOSFET, QB1. BG1 is designed to drive up to
10,000pF of gate capacitance directly. If RUN/SS1 goes
low, BG1 will go low, turning off QB1. If FAULT mode is
tripped, BG1 will go high and stay high, keeping QB1 on
until the power is cycled.
TG1 (Pin 4): Controller 1 Top Gate Drive. The TG1 pin
drives the gate of the top N-channel MOSFET, QT1. The
TG1 driver draws power from the BOOST1 pin and returns
to the SW1 pin, providing true floating drive to QT1. TG1
is designed to drive up to 10,000pF of gate capacitance
directly. In shutdown or fault modes, TG1 will go low.
SW1 (Pin 5): Controller 1 Switching Node. SW1 should be
connected to the switching node of converter 1. The TG1
driver ground returns to SW1, providing floating gate
drive to the top N-channel MOSFET switch, QT1. The
voltage at SW1 is compared to IMAX1 by the current limit
comparator while the bottom MOSFET, QB1, is on.
IMAX1 (Pin 6): Controller 1 Current Limit Set. The IMAX1
pin sets the current limit comparator threshold for
controller 1. If the voltage drop across the bottom MOSFET,
QB1, exceeds the magnitude of the voltage at IMAX1,
controller 1 will go into current limit. The IMAX1 pin has an
internal 10µA current source pull-up, allowing the current
threshold to be set with a single external resistor to PGND.
This current setting resistor should be Kelvin connected to
the source of QB1. See the Current Limit Programming
section for more information on choosing RIMAX.
FCB (Pin 7): Force Continuous Bar. The FCB pin forces
both converters to maintain continuous synchronous
operation regardless of load when the voltage at FCB
drops below 0.8V. FCB is normally tied to VCC. To force
continuous operation, tie FCB to SGND. FCB can also be
connected to a feedback resistor divider from a secondary
winding on one converter’s inductor to generate a third
regulated output voltage. Do not leave FCB floating.
RUN/SS1 (Pin 8): Controller 1 Run/Soft-Start. Pulling
RUN/SS1 to SGND will disable controller 1 and turn off
both of its external MOSFET switches. Pulling both
RUN/SS pins down will shut down the entire LTC1703,
dropping the quiescent supply current below 100µA. A
capacitor from RUN/SS1 to SGND will control the turn-on
time and rate of rise of the controller 1 output voltage at
power-up. An internal 3.5µA current source pull-up at
RUN/SS1 pin sets the turn-on time at approximately
50ms/µF.
COMP1 (Pin 9): Controller 1 Loop Compensation. The
COMP1 pin is connected directly to the output of the first
controller’s error amplifier and the input to the PWM
comparator. An RC network is used at the COMP1 pin to
compensate the feedback loop for optimum transient
response.
SGND (Pin 10): Signal Ground. All internal low power
circuitry returns to the SGND pin. Connect to a low
impedance ground, separated from the PGND node. All
feedback, compensation and soft-start connections should
return to SGND. SGND and PGND should connect only at
a single point, near the PGND pin and the negative plate of
the CIN bypass capacitor.
FB1 (Pin 11): Controller 1 Feedback Input. The loop
compensation network for controller 1 should be con-
nected to FB1. FB1 is connected internally to the VID
resistor network to set the output voltage at side 1.
SENSE (Pin 12): Output Sense. Connect to VOUT1.
VID0 to VID4 (Pins 13 to 17): VID Programming Inputs.
These are logic inputs that set the output voltage at side 1
to a preprogrammed value (see Table 1). VID4 is the MSB,
VID0 is the LSB. The codes selected by the VIDn inputs
correspond to the Intel Mobile VID specification. Each
5
5 Page 
LTC1703
APPLICATIO S I FOR ATIO
This constant frequency operation brings with it a couple
of benefits. Inductor and capacitor values can be chosen
with a precise operating frequency in mind and the feed-
back loop components can be similarly tightly specified.
Noise generated by the circuit will always be in a known
frequency band with the 550kHz frequency designed to
leave the 455kHz IF band free of interference. Subharmonic
oscillation and slope compensation, common headaches
with constant frequency current mode switchers, are
absent in voltage mode designs like the LTC1703.
During the time that QT is on, its source (the SW pin) is at
VIN. VIN is also the power supply for the LTC1703. How-
ever, QT requires VIN + VGS(ON) at its gate to achieve
minimum RON. This presents a problem for the LTC1703—
it needs to generate a gate drive signal at TG higher than
its highest supply voltage. To accomplish this, the TG
driver runs from floating supplies, with its negative supply
attached to SW and its power supply at BOOST. This allows
it to slew up and down with the source of QT. In combination
with a simple external charge pump (Figure 2), this allows
the LTC1703 to completely enhance the gate of QT without
requiring an additional, higher supply voltage.
The two channels of the LTC1703 run from a common
clock, with the phasing chosen to be 180° from side 1 to
side 2. This has the effect of doubling the frequency of the
switching pulses seen by the input bypass capacitor,
significantly lowering the RMS current seen by the capaci-
tor and reducing the value required (see the 2-Phase
section).
Feedback Amplifier
Each side of the LTC1703 senses the output voltage at
VOUT with an internal feedback op amp (see Block Dia-
gram). This is a real op amp with a low impedance output,
85dB open-loop gain and 25MHz gain-bandwidth product.
The positive input is connected internally to an 800mV
reference, while the negative input is connected to the FB
pin. The output is connected to COMP, which is in turn
connected to the soft-start circuitry and from there to the
PWM generator.
Unlike many regulators that use a resistor divider con-
nected to a high impedance feedback input, the LTC1703
is designed to use an inverting summing amplifier
PVCC BOOST
TG
SW
LTC1703
BG
PGND
VIN
+
DCP CIN
CCP
1µF
QT LEXT
VOUT
+
QB COUT
1703 F02
Figure 2. Floating TG Driver Supply
topology with the FB pin configured as a virtual ground.
This allows flexibility in choosing pole and zero locations
not available with simple gm configurations. In particular,
it allows the use of “type 3” compensation, which pro-
vides a phase boost at the LC pole frequency and signifi-
cantly improves loop phase margin (see Figure 3). The
Feedback Loop/Compensation section contains a de-
tailed explanation of type 3 feedback loops. Note that side
1 of the LTC1703 includes R1 and RB internally as part
of the VID DAC circuitry.
MIN/MAX COMPARATORS
Two additional feedback loops keep an eye on the primary
feedback amplifier and step in if the feedback node moves
±5% from its nominal 800mV value. The MAX comparator
(see Block Diagram) activates whenever FB rises more
than 5% above 800mV. It immediately turns the top
MOSFET (QT) off and the bottom MOSFET (QB) on and
keeps them that way until FB falls back within 5% of its
nominal value. This pulls the output down as fast as pos-
sible, preventing damage to the (often expensive) load. If
FB rises because the output is shorted to a higher supply,
QB will stay on until the short goes away, the higher supply
COMP
+
FB
–
0.8V
FB
C2
C3
R3
R1
RB
VOUT
R2 C1
1703 F03
Figure 3. “Type 3” Feedback Loop (Side 2 Shown)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC1703.PDF ] | |
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