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PDF Am79C874 Data sheet ( Hoja de datos )
| Número de pieza | Am79C874 | |
| Descripción | NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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PRELIMINARY
Am79C874
NetPHY™-1LP Low Power 10/100-TX/FX Ethernet Transceiver
DISTINCTIVE CHARACTERISTICS
s 10/100BASE-TX Ethernet PHY device with
100BASE-FX fiber optic support
s Typical power consumption of 0.3 W
s Sends/receives data reliably over cable lengths
greater than 130 meters
s MII mode supports 100BASE-X and 10BASE-T
s 7-Wire (General Purpose Serial Interface (GPSI))
mode supports 10BASE-T
s Three PowerWise™ management modes (from
300 mW typical)
— Power down: only management responds
Typical power = 3 mW
— Unplugged: no cable, no receive clock
Typical power = 100 mW
— Idle wire: no wire signal, no receiver power
Typical power = 285 mW; MAC saves over
100 mW
s Supports 1:1 or 1.25:1 transmit transformer
— Using a 1.25:1 ratio saves 20% transmit
power consumption
— No external filters or chokes required
s Waveshaping – no external filter required
s Full and half-duplex operation with full-featured
Auto-Negotiation function
s LED indicators: Link, TX activity, RX activity,
Collision, 10 Mbps, 100 Mbps, Full or Half
Duplex
s MDIO/MDC operates up to 25 MHz
s Automatic Polarity Detection
s Built-in loopback and test modes
s Single 3.3-V power supply with 5-V I/O tolerance
s 12 mm x 12 mm 80-pin TQFP package
s Support for industrial temperature
(-40°C to +85°C)
GENERAL DESCRIPTION
The Am79C874 NetPHY-1LP device provides the phys-
ical (PHY) layer and transceiver functions for one
10/100 Mbps Ethernet port. It delivers the dual benefits
of CMOS low power consumption and small package
size. Operating at 3.3 V, it consumes only 0.3 W. Three
power management modes provide options for even
lower power consumption levels. The small 12x12 mm
80-pin PQL package conserves valuable board space
on adapter cards, switch uplinks, and embedded Ether-
net applications.
The NetPHY-1LP 10/100 Mbps Ethernet PHY device is
IEEE 802.3 compliant. It can receive and transmit data
reliably at over 130 meters. It includes on-chip input fil-
tering and output waveshaping for unshielded twisted
pair operation without requiring external filters or
chokes. The NetPHY-1LP device can use 1:1 isolation
transformers or 1.25:1 isolation transformers. 1.25:1
isolation transformers provide 20% lower transmit
power consumption. A PECL interface is available for
100BASE-FX applications.
Interface to the Media Access Controller (MAC) layer is
established via the standard Media Independent Inter-
face (MII), a 5-bit symbol interface, or a 7-wire (GPSI)
interface. Auto-Negotiation determines the network
speed and full or half-duplex operation. Automatic po-
larity correction is performed during Auto-Negotiation
and during 10BASE-T signal reception.
Multiple LED pins are provided for front panel status
feedback. One option is to use two bi-color LEDs to
show when the device is in 100BASE-TX or 10BASE-T
mode (by illuminating), Half or Full Duplex (by the
color), and when data is being received (by blinking).
Individual LEDs can indicate link detection, collision
detection, and data being transmitted.
The NetPHY-1LP device needs only one external 25-
MHz oscillator or crystal because it uses a dual-speed
clock synthesizer to generate all other required clock
domains. The receiver has an adaptive equalizer/DC
restoration circuit for accurate clock/data recovery from
the 100BASE-TX signal.
The NetPHY-1LP device is available in the commercial
(0°C to +70°C) or industrial (-40°C to +85°C) tempera-
ture ranges. The industrial temperature range is well
suited to environments, such as enclosures with re-
stricted air flow or outdoor equipment.
Publication# 22235 Rev: I Amendment/0
Refer to AMD’s Website (www.amd.com) for the latest information. Issue Date: April 2001
1 page  
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Am79C874
5
5 Page 
PRELIMINARY
TX_ER/TXD[4]
Transmit Error
Input
When TX_ER is asserted, it will cause the 4B/5B en-
coding process to substitute the transmit error code-
group /H/ for the encoded data word.
This pin becomes the higher-order bit of the transmit 5-
bit code group in PCS bypass (PCSBP=HIGH) mode.
This input is ignored in the 10BASE-T operation.
TX_CLK/10TXCLK/PCSBPCLK
Transmit Clock
Output, High Impedance
A free-running clock which provides timing reference
for TX_EN, TX_ER, and TXD[3:0] signals. It is 25 MHz
in 100BASE-TX/FX and 2.5 MHz in 10BASE-T.
When 7-wire GPSI mode is enabled, this pin will pro-
vide a 10 MHz transmit clock for 10BASE-T operation.
When the cable is unplugged, the 10TXCLK ceases
operation.
When working in PCSBP mode, this pin will provide a
25 MHz clock for 100BASE-TX operation, and 20 MHZ
clock for 10BASE-T operation. TX_CLK is high imped-
ance when the ISO pin is enabled.
TX_EN/10TXEN
Transmit Enable
Input
The TX_EN pin is asserted by the MAC to indicate that
data is present on TXD[3:0].
When 7-wire 10BASE-T mode is enabled, this pin is the
transmit enable signal.
TXD[3:1]
Transmit Data
Input
The MAC will source TXD[3:1] to the PHY. The data will
be synchronous with TX_CLK when TX_EN is as-
serted. The PHY will clock in the data based on the ris-
ing edge of TX_CLK.
TXD[0]/10TXD
Transmit Data[0]/10 Mbps Transmit Data
Input
The MAC will source TXD[0] to the PHY. The data will
be synchronous with TX_CLK when TX_EN is as-
serted. The PHY will clock in the data based on the ris-
ing edge TX_CLK.
When 7-wire 10BASE-T mode is enabled, this pin will
transmit serial data.
COL/10COL
Collision
Output, High Impedance
COL is asserted high when a collision is detected on
the media. COL is also used for the SQE test function
in 10BASE-T mode.
10COL is asserted high when a collision is detected
during 7-wire interface mode.
CRS/10CRS
Carrier Sense
Output, High Impedance
CRS is asserted high when twisted pair media is non-
idle. This signal is used for both 10BASE-T and
100BASE-X. In full duplex mode, CRS responds only to
RX activity. In half duplex mode, CRS responds to both
RX and TX activity.
10CRS is used as the carrier sense output for the
7-wire interface mode.
Miscellaneous Functions
PCSBP
PCS Bypass
Input, Pull-Down
The 100BASE-TX PCS as well as scrambler/descram-
bler will be bypassed when PCSBP is pulled high via a
10 kW resistor. TX_ER will become TXD[4] and RX_ER
will become RXD[4].
In 10 Mbps PCS bypass mode, the MII signals are not
valid. The signals that interface to the MAC (i.e.,
DECPC 21143) are located on pins 14 to 19. The sig-
nals are defined as follows:
— 10RXD± are the differential receive outputs to
the MAC.
— 10TXD± are the differential transmit inputs from
the MAC.
— 10TXD++/10TXD-- are the differential pre-
emphasis transmit outputs from the MAC.
When left unconnected, the device operates in MII or
GPSI mode.
ISODEF
Isolate Default
Input, Pull-Down
This pin is used when multiple PHYs are connected to
a single MAC. When it is pulled high via a 10 kW resis-
tor, the MII interface will be high impedance. The status
of this pin will be latched into MII Register 0, bit 10 after
reset.
When this pin is left unconnected, the default condition
of the MII output pins are not in the high impedance
state.
ISO
Isolate
Input, Pull-Down
The MII output pins will become high impedance when
ISO is pulled high via a 10 kW resistor. However, the MII
input pins will still respond to data. This allows multiple
PHYs to be attached to the same MII interface. The
same isolate condition can also be achieved by assert-
ing MII Register 0, bit 10. In repeater mode, ISO will not
tri-state the CRS pin.
When this pin is left unconnected, the MII output pins
are not in the high impedance state.
Am79C874
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Am79C874.PDF ] | |
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