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PDF CXP88340 Data sheet ( Hoja de datos )
| Número de pieza | CXP88340 | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP88340/88348
CMOS 8-bit Single Chip Microcomputer
Description
The CXP88340/88348 is a CMOS 8-bit microcomputer
100 pin QFP (Plastic)
which consists of A/D converter, serial interface,
timer/counter, time-base timer, high precision timing
pattern generation circuit, PWM output, VISS/VASS
circuit, 32kHz timer/counter, remote control receiving
circuit, VSYNC separator and the measurement circuit
which measure signals of capstan FG and drum
FG/PG and other servo systems, as well as basic
configurations like 8-bit CPU, ROM, RAM and I/O
port. They are integrated into a single chip.
Also, the CXP88340/88348 provides sleep/stop
functions which enable to lower power consumption.
Structure
Features
Silicon gate CMOS IC
• A wide instruction set (213 instructions) which covers various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle 250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated ROM capacity 40K bytes (CXP88340)
48K bytes (CXP88348)
• Incorporated RAM capacity 1376 bytes
• Peripheral functions
— A/D converter
8 bits, 12 channels, successive approximation system
(Conversion time of 20µs/16MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channnel
Incorporated two-wire 8-bit and 8-stage FIFO (Auto transfer for
1 to 8 bytes), 1 channel
— Timer
8-bit timer/counter, 2 channels
19-bit time-base timer
32kHz timer/counter
— High precision timing pattern generation PPG: Maximum of 19 pins 32 stages programmable
circuit
RTG: 5 pins, 1 channel
7-bit, 10-satge FIFO (RECCTL control/ATC control),
1 channel
— PWM/DA gate output
PWM: 12 bits, 2 channels (Repetitive frequency 62.5kHz at 16MHz)
DA gate pulse output: 13 bits, 2 channels
— Analog signal input circuit
PBCTL amplifier circuit
Reel FG comparator
— CTL write/rewrite circuit
Recording current control circuit
— Servo input control
Capstan FG, Drum FG/PG, CTL, Reel FG input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14 bits, 1 channel
— VISS/VASS circuit
Pulse duty auto detection circuit
— Remote control receiving circuit
8-bit pulse measurement counter, 6-stage FIFO
— Tri-state output
PPG output 2 pins
— High speed head switching circuit
• Interruption
22 factors, 15 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
100-pin plastic QFP
• Piggy/evaluation chip
CXP88400 100-pin ceramic PQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98835-PS
1 page  
CXP88340/88348
Description
AN0 to AN3
PF0/AN4
to
PF3/AN7
PF4/AN8
to
PF7/AN11
PG0/CFG
PG1/DFG
PG2/DPG
PG3/EC/
INT2
PH0/SCL0
PH1/SCL1
PH2/SDA0
PH3/SDA1
PH4 to PH7
PI0/INT0
PI1 to PI7
I/O
Input
Input/Input
Output/Input
Input/Input
Input/Input/Input
I/O/I/O
Output
I/O/Input
I/O
Description
(Port F)
Lower 4 bits are for inputs; upper 4 bits are for
outputs. Lower 4 bits also serve as standby
release input pins.
(8 pins)
Analog input pin to
A/D converter.
(12 pins)
Capstan FG input pin.
Drum FG input pin.
(Port G)
4-bit input port.
(4 pins)
Drum PG input pin.
External event input
pin for
timer/counter.
Input pin to request
external interruption.
Active when falling
edge.
(Port H)
8-bit I/O port. Upper four Serial clock (CH2) I/O pin.
bits are for outputs. I/O
can be set in a unit of
Serial data (CH2) I/O pin.
single bits for lower four
bits.
Lower four bits are N-ch open drain outputs and which can drive 12mA
sink current.
Upper four bits are for outputs; N-ch open drain output of medium drive
voltage (12V) and large current (12mA).
(8 pins)
(Port I)
8-bit I/O port. I/O can be
Input pin to request external interruption.
Active when falling edge.
set in a unit of single bits.
Function as standby release input can be set in a unit of single bits.
(8 pins)
RFG0, RFG1 Input
ANOUT
Output
CTLFAMPO Output
CTLSAMPI
Input
CTLAGND
Output
CTLFAMPI (–)
CTLFAMPI (+)
Input
HEADL (–)
HEADL (+)
Output
CTLHEAD (–)
CTLHEAD (+)
I/O
AMPVSS
AMPVDD
Input ports. (2 pins)
Output port. (1 pin)
Output port. (1 pin)
Input port. (1 pin)
Output port. (1 pin)
Reel FG input pin.
Internal waveform output pin of analog circuit.
PBCTL signal 1st amplifier output pin.
PBCTL signal 2nd amplifier input pin.
Smoothing capacitor connecting pin.
Input ports. (2 pins)
Input PBCTL signal with capacitor coupled.
Output ports. (2 pins)
During playback, connect to CTLHEAD (–)
and CTLHEAD (+) with internal switch.
I/O ports. (2 pins)
During playback, input pin of PBCTL signal;
during recording, output pin of PBCTL signal.
Analog signal input circuit GND pin.
Analog signal input circuit power supply pin.
–5–
5 Page 
CXP88340/88348
Pin
AN0
to
AN3
4 pins
PF0/AN4
to
PF3/AN7
Port F
4 pins
Port F
Circuit format
Input multiplexer
IP
A/D converter
Input multiplexer
IP A/D converter
Internal data bus
RD (Port F)
After a reset
Hi-Z
Hi-Z
PF4/AN8
to
PF7/AN11
4 pins
Port F data
Internal data bus
RD (Port F)
Port/AD select
"1" after a reset
IP
Input multiplexer
A/D converter
Port G
PG0/CFG
PG1/DFG
PG2/DPG
3 pins
PG3/EC/INT2
Port G
1 pin
Schmitt input
IP
Power ON/OFF control
Servo input
Internal data bus
RD (Port G)
Schmitt width selection
Schmitt input
IP
Internal data bus
RD (Port G)
Hi-Z
Hi-Z
Hi-Z
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXP88340.PDF ] | |
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